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| ? 2012 - 2015 microchip technology inc. ds00001682c-page 1 general description the usb5537b hub is a 7-port superspeed/hi-speed, low-power, configurable hub controller family fully com- pliant with the usb 3.0 specification . the usb5537b supports 5 gbps superspeed (ss), 480 mbps hi- speed (hs), 12 mbps full-speed (fs) and 1.5 mbps low-speed (ls) usb signaling for complete coverage of all defined usb operating speeds. the usb5537b supports usb 2.0 speeds through its usb 2.0 hub controller. the new superspeed hub con- troller (available on 4 of the 7 ports) operates in parallel with the usb 2.0 controller, so the 5 gbps superspeed data transfers are not affected by the slower usb 2.0 traffic. the usb5537b supports battery charging on a per port basis. on battery charging enabled ports, the devices provide automatic usb data line handshaking. the handshaking supports usb 1.2 charging downstream port (cdp), dedicated charging port (dcp) and non- usb 1.2 devices. the usb5537b is configured for operation through internal default settings, where custom configurations are supported through an on-chip otp rom, an exter- nal spi rom, or smbus. product features usb 3.0 compliant 5 gbps, 480 mbps, 12 mbps and 1.5 mbps operation, usb pins are 5 v toler- ant - integrated terminati on and pull-up/pull-down resistors four downstream usb 3.0 ports three additional usb 2.0 ports for use cases where ss is not required supports battery charging of most popular battery powered devices - usb-if battery charging rev. 1.2 support (dcp & cdp) - apple portable product charger emulation - blackberry charger emulation - chinese yd/t 1591-2006 charger emulation - chinese yd/t 1591-2009 charger emulation - supports additional portable devices emulates portable/handheld native wall chargers - charging profiles emulate a handheld devices wall charger to enable fast charging (minutes vs. hours) enables charging from a mobile platform that is off support tablets high current requirements optimized for low-power operation and low ther- mal dissipation vendor specific messaging (vsm) support for firmware upload over usb configuration via otp rom, spi rom, or smbus on-chip 8051 c manages vbus, and other hub signals 8 kb ram, 32 kb rom one time programmable (otp) rom: 8 kbit - includes on-chip charge pump single 25 mhz xtal or clock input for all on-chip pll and clocking requirements supports jtag boundary scan phyboost (usb 2.0) - selectable drive strength for improved signal integrity varisense (usb 2.0) - controls the receiver sensitivity enabling four programmable levels of usb signal receive sensitivity ietf rfc 4122 compliant 128-bit uuid software features compatible with microsoft windows 7, vista, xp, mac osx10.4+, and linux hub drivers usb5537b 7-port ss/hs usb hub controller downloaded from: http:///
usb5537b ds00001682c-page 2 ? 2012 - 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 3 usb5537b table of contents 1.0 introduction ..................................................................................................................................................................................... 4 2.0 block diagram ............................................................................................................. .................................................................... 6 3.0 pin information ................................................................................................................................................................................ 7 4.0 standard interface connections ............................................................................................ ....................................................... 13 5.0 functional operation ..................................................................................................................................................................... 24 6.0 dc parameters ............................................................................................................................................................................. 63 7.0 ac specifications .......................................................................................................................................................................... 67 8.0 package drawing ........................................................................................................... ............................................................... 70 appendix a: data sheet revision history ........................................................................................................................................... 72 appendix b: acronyms ........................................................................................................................................................................ 74 appendix c: references ..................................................................................................................................................................... 75 the microchip web site ........................................................................................................ .............................................................. 76 customer change notification service ............................................................................................................................................... 76 customer support ............................................................................................................................................................................... 76 product identification system ................................................................................................. ............................................................ 77 downloaded from: http:/// usb5537b ds00001682c-page 4 ? 2012 - 2015 microchip technology inc. 1.0 introduction 1.1 conventions within this manual, the following abbreviation s and symbols are used to improve readability. 1.2 overview the usb5537b hub is a 7-port, low-power, config urable hub controller fully compliant with the usb 3.0 specification 2. the usb5537b supports 5 gbps superspeed (ss), 480 mbps hi-speed (hs), 12 mbps full-speed (fs) and 1.5 mbps low-speed (ls) usb signaling for comple te coverage of all defined usb operating speeds. all required resistors on the usb ports are integrated into the hub. this includes all series termination resistors and all required pull-down and pull-up resistors on d+ and d- pins . the over-current sense inputs for the downstream facing ports have internal pull-up resistors. the usb5537b hub includes programmable features such as: multitrak tm technology (usb 2.0): implements a dedicated transaction translator (tt) for each port. dedi- cated tts help maintain consistent full-speed data throu ghput regardless of the num ber of active downstream connections. portswap (usb 2.0): allows direct alignment of usb signals (d+/d-) to connectors to avoid uneven trace length or crossing of the usb differential signals on the pcb. phyboost (usb 2.0): enables 4 programmable levels of usb si gnal drive strength in downstream port transceiv- ers (hs, fs, ls usb only). phyboost will al so attempt to restore usb signal integrity. example description bit name of a single bit within a field field.bit name of a single bit (bit) in field xy range from x to y, inclusive bits[m:n] groups of bits from m to n, inclusive pin pin name zzzzb binary number (value zzzz) 0xzzz hexadecimal number (value zzz) zzh hexadecimal number (value zz) rsvd reserved memory location. must write 0, read value indeterminate code instruction code, or api function or parameter multi word name used for multiple words that are considered a single unit, such as: resource allocate message, or connection label , or decrement stack pointer instruction. section name section or document name. xd o n t c a r e ? 2012 - 2015 microchip technology inc. ds00001682c-page 5 usb5537b as shown on the product identification system page, three usb5537b firmware vers ions are available: -5000, -6070, and -6080. these options differ in the following ways: the dynamic charging port feature and related dyncpdis_ n pin function are only available on the -6070 and - 6080 devices. refer to section 5.1.3, "dynamic charging port (6070 and 6080 only)" for additional details. the trst/dyncpdis_n/ucs_smbalert_n pin buffer type is ipu in the -6070 and -6080 devices and i in the -5000 device. refer to pin information on page 7 for additional details. the global suspend power consumption has been significantly lowered in the -6070 and -6080 device. refer to section 6.3, "power consumption" for additional details. the three usb 2.0 ports are configured as removable by default in the -6070 device. the three usb 2.0 ports are configured as non-removable by default in the -5000 and -6080 devices. 1.3 configurable features the usb5537b hub controller provides a de fault configuration that is sufficient for most applications. when initialized in the default configuration, the following features may be configured: downstream non-removable ports, where the hub will automatically report as a compound device downstream disabled ports downstream port power control and over-current detection on a ganged or individual basis usb signal drive strength usb differential pair pin location the usb5537b hub controllers can alternatively be configur ed by otp or as an smbus slave device. when configured by an otp or over smbus, the followin g configurable feat ures are provided: support for compound devices on a port-by-port basis selectable over-current sensing and port power control on an individual or ganged basis to match the circuit board component selection customizable vendor id, product id, and device id configurable delay time for filtering the over-current sense inputs indication of the maximum current that t he hub consumes from the usb upstream port indication of the maximum current required for the hub controller custom string descriptors (up to 30 characters): product, manufacturer, and serial number note: at the time of this writing, products with a usb ho st (or products such as docking stations with usb hubs that must be submitted with an at tached host enabled platform) are eligible for usb logo with a mixture of usb2.0 and usb3.0 ports. an example of such a pr oduct is a dedicated docking station that can only be used with a specific model or family of laptops. in this example, the docking st ation is submitted for usb logo testing with a laptop and it is tested as a system. usb devices containing a hub with an exposed upstream port that can be plugged into any host plat form through usb cables and connectors (examples are usb enabled monitors, printers, hard drives, etc.) ar e not eligible for logo with a mixture of usb 3.0 and usb 2.0 ports. these devices will need to consume the usb 2.0-only ports internally in order to be eligible for a usb logo. downloaded from: http:/// usb5537b ds00001682c-page 6 ? 2012 - 2015 microchip technology inc. 2.0 block diagram figure 2-1: usb5537b block diagram usb 3.0 hub controller tx ss phy rx ss phy usb2.0 phy usb 2.0 hub controller buffer hs/fs/ls routing logic common block & pll registers & hub i/o vbus control buffer tx ss phy rx ss phy usb2.0 phy buffer buffer tx ss phy rx ss phy usb2.0 phy buffer buffer tx ss phy rx ss phy usb2.0 phy buffer buffer tx ss phy rx ss phy usb2.0 phy buffer buffer upstream usb port downstream usb port 1 downstream usb port 2 downstream usb port 3 downstream usb po rt 4 embedded 8051 c registers & hub i/o 32k rom 8k ram apb bus xdata xdata to apb bridge downstream rx ss bus downstream tx ss bus reset & 8051 boot seq. 2k otp spi master timer spi usb2.0 phy downstream usb 2.0 ports 5, 6, & 7 usb2.0 phy usb2.0 phy downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 7 usb5537b 3.0 pin information this chapter outlines the pinni ng configurations for each chip. the detailed pin descriptions are listed by function in sec- tion 3.2, "pin descriptions (grouped by function)," on page 8 . 3.1 pin configurations figure 3-1: usb5537b 72-pin qfn ground pad (must be connected to vss with a via field) usb5537b (top view qfn-72) usb2dp_dn2 70 usb3dm_rxdn2 69 usb3dp_rxdn2 68 vdd12 67 usb3dm_txdn2 66 usb3dp_txdn2 65 prt_pwr6/prt_ctl6 64 prt_pwr7/prt_ctl7 63 usb2dm_dn1 62 usb3dm_rxdn1 60 usb3dp_rxdn1 59 vdd12 58 usb3dm_txdn1 57 usb3dp_txdn1 56 55 usb2dp_dn1 61 vdd33 72 usb2dm_dn2 71 usb2dm_dn5 16 usb2dp_dn5 15 usb2dm_dn4 14 usb2dp_dn4 13 usb3dm_rxdn4 12 usb3dp_rxdn4 11 vdd12 10 usb3dm_txdn4 9 usb3dp_txdn4 8 usb2dp_dn3 6 usb3dm_rxdn3 5 usb3dp_rxdn3 4 vdd12 3 usb3dm_txdn3 2 usb3dp_txdn3 1 usb2dm_dn3 7 trst/dyncpdis_n/ ucs_smbalert_n 17 tck/ocs1 18 prt_pwr2/prt_ctl2 36 prt_pwr1/prt_ctl1 35 34 33 spi_di 32 spi_do 31 spi_clk 30 spi_ce_n 29 vdd12 28 prt_pwr5/prt_ctl5/ sm_dat 27 test 26 reset_n 25 tdi/ocs3 24 tdo/ocs4 23 tms/ocs2 22 vdd33 21 prt_pwr4/prt_ctl4 20 prt_pwr3/prt_ctl3 19 vdd33 54 rbias 53 xtalin/clk_in 52 xtalout 51 usb3dm_rxup 50 usb3dp_rxup 49 vdd12 48 usb3dm_txup 47 usb3dp_txup 46 usb2dm_up 45 usb2dp_up 44 usb2dp_dn7 43 usb2dm_dn7 42 usb2dp_dn6 41 usb2dm_dn6 40 vdd12 39 vbus 38 vdd33 37 sm_clk atest vdd12 indicates pins on the bottom of the device. downloaded from: http:/// usb5537b ds00001682c-page 8 ? 2012 - 2015 microchip technology inc. 3.2 pin descriptions (grouped by function) an n at the end of a signal name indicates that the active (a sserted) state occurs when the signal is at a low voltage level. when the n is not present, the signal is asserted when it is at a high voltage level. the terms assertion and nega- tion are used exclusively in order to avoid confusion when wo rking with a mixture of active low and active high signals. the term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate, or negatio n, indicates that a signal is inactive. table 3-1: usb5537b pin descriptions symbol buffer type description usb 3.0 interface usb3dp_txup io-u usb 3 upstream upstream superspeed transmit data plus usb3dm_txup io-u usb 3 upstream upstream superspeed transmit data minus usb3dp_rxup io-u usb 3 upstream upstream superspeed receive data plus usb3dm_rxup io-u usb 3 upstream upstream superspeed receive data minus usb3dp_txdn[4:1] io-u usb 3 downstream downstream superspeed transmit data plus for ports 1 through 4. usb3dm_txdn[4:1] io-u usb 3 downstream downstream superspeed transmit data minus for ports 1 through 4. usb3dp_rxdn[4:1] io-u usb 3 downstream downstream superspeed receive data plus for ports 1 through 4. usb3dm_rxdn[4:1] io-u usb 3 downstream downstream superspeed receive data minus for ports 1 through 4. usb 2.0 interface usb2dp_up io-u usb bus data these pins connect to the upstream usb bus data signals. usb2dm_up io-u usb bus data these pins connect to the upstream usb bus data signals. usb2dp_dn[7:1] io-u hi-speed usb data downstream hi-speed data plus for ports 1 through 7. usb2dm_dn[7:1] io-u hi-speed usb data downstream hi-speed data minus for ports 1 through 7. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 9 usb5537b usb port control prt_pwr[7:1]/ prt_ctl[7:1] o12 usb power enable enables power to usb peripheral devices downstream. note: this pin also provides conf iguration strap functions. see note 3-1 . vbus i upstream vbus power detect this pin can be used to detect the st ate of the upstream bus power. the device monitors this pin to determine when to assert the internal d+ pull- up resistor (signaling a connect event). when designing a detachable hub, this pin should be connected to vbus on the upstream port via a 2:1 voltage divider. two 100 k ? resistors are suggested. for self-powered applications with a pe rmanently attached host, this pin must be connected to a dedicated host control output, or connected to the 3.3 v domain that pow ers the host (typically vdd33 ). spi interface spi_ce_n o12 spi enable spi_clk o12 spi clock spi_do o12 spi serial data out the output for the spi port. note: this pin also provides conf iguration strap functions. see . spi_di i spi serial data in the spi data in to the controller from the rom. this pin has a weak internal pull-down applied at all times to prevent floating. jtag/ocs interface trst ipu ( note 3-4 ) jtag asynchronous reset note: if using the smbus interface, a pull-up on this signal will enable legacy mode, while leaving it unconnected or pulled-down will enable advanced mode. dyncpdis_n dynamic charging port disable this active-low signal is used to globally disable charging port support. note: this signal available in -6070 and -6080 versions only ucs_smbalert_n ucs1002 smbus alert when charging port is enabled and smbus devices are used, this signal acts as an active-low smbus alert. tck i jtag clock this input is used for jtag boundary scan and has a weak pull-down. it can be left floating or grounded when not used. if the jtag is connected, then this signal will be detected high, and the software disables the pull up after reset. ocs1 over-current sense 1 input from external current monitor indicating an over-current condition. note: this pin also provides conf iguration strap functions. see note 3-3 . table 3-1: usb5537b pin descriptions (continued) symbol buffer type description downloaded from: http:/// usb5537b ds00001682c-page 10 ? 2012 - 2015 microchip technology inc. tms i jtag tms used for jtag boundary scan. ocs2 over-current sense 2 input from external current monitor indicating an over-current condition. note: this pin also provides conf iguration strap functions. see note 3-3 . tdi i jtag tdi used for jtag boundary scan. ocs3 over-current sense 3 input from external current monitor indicating an over-current condition. note: this pin also provides conf iguration strap functions. see note 3-3 . tdo o12 jtag tdo used for jtag boundary scan. ocs4 over-current sense 4 input from external current monitor indicating an over-current condition. note: this pin also provides conf iguration strap functions. see note 3-3 . misc reset_n is reset input the system uses this active low signa l to reset the chip. the active low pulse should be at least 1 ? s wide. xtalin iclkx crystal input: 25 mhz crystal. this pin connects to either one terminal of the crystal or to an external 25 mhz clock when a crystal is not used. clk_in external clock input this pin connects to either one terminal of the crystal or to an external 25 mhz clock when a crystal is not used. xtalout oclkx crystal output the clock output, providing a crystal 25 mhz. when an external clock source is used to drive xtalin/clkin , this pin becomes a no connect. test ipd test pin treat as a no connect pin or connect to ground. no trace or signal should be routed or at tached to this pin. rbias i-r usb transceiver bias a12.0 k ? (+/- 1%) resistor is attached from ground to this pin to set the transceivers internal bias settings. atest a analog test pin this signal is used for testing the chip and must always be connected to ground. sm_clk i/o12 smbus clock sm_dat i/o12 smbus data pin note: this pin is muxed with prt_ctrl5 table 3-1: usb5537b pin d escriptions (continued) symbol buffer type description downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 11 usb5537b note 3-1 the prt_pwr[4:1] pins can optionally prov ide additional configuration strap functions to enable/disable the associated port and configure its ba ttery charging capabilitie s. configuration strap values are latched on device reset. ta b l e 3 - 2 details the functions associated with the various strap settings. strapping features are enabled by default and can be optionally disabled via the pro-touch software programming tool. for additional information on t he pro-touch programming tool, contact your local sales representative. strapping functions are not supported for desig ns that support ocs but not power switching. note 3-2 the spi_do pin provides an additional spi_spd_ sel configuration strap function. spi_spd_sel selects between the 30mhz spi mode when pulled-down to ground (default) and the 60mhz spi mode when pulled-up to vdd33. the spi_spd_sel strap value is latched on power-on reset (por) or reset_n deassertion. note 3-3 the ocs[4:1] pins can optionally provide additi onal configuration strap functions. to set the associated port into the non-removable state, the ocs pin must be configured with a pull-down (<10 k ?? to vss). otherwise, the port will be configured in the removable state. configuration strap values are latched on device reset. strapping features are enabled by default and can be optionally disabled via the pro-touch software programming tool. for additional information on t he pro-touch programming tool, contact your local sales representative. strapping functions are not supported for desig ns that support ocs but not power switching. note 3-4 this pin has an internal pull-up only in the -607 0 and -6080 versions. the internal pull-up is only active after the smbus mode (legacy/advanced) configuration strap has been sampled at por or reset. the -5000 version is an i type buffer. digital and power (12 pins and 1 ground pad) (4) vdd33 3.3 v power (8) vdd12 1.25 v power vss ground pad this exposed pad is the devices only connection to vss and the primary thermal conduction path. conne ct to an appropriate via field. table 3-2: prt_pwr[4 :1 ] configuration strap states prt_pwr[4:1] strap setting port state battery charging no pull-up or pull-down enabled disabled pull-down: <10 k ?? to vss disabled n/a pull-up: <10 k ?? and >1 k ? to vdd33 enabled enabled table 3-1: usb5537b pin descriptions (continued) symbol buffer type description downloaded from: http:/// usb5537b ds00001682c-page 12 ? 2012 - 2015 microchip technology inc. 3.3 buffer type descriptions table 3-3: buffer type descriptions buffer type description i input i/o input/output ipd input with internal weak pull-down resistor ipu input with internal weak pull-up resistor is input with schmitt trigger o12 output 12 ma i/o12 input/output buffer with 12 ma sink and 12 ma source i/osd12 open drain with schmitt trigger and 12 ma sink. iclkx xtal clock input oclkx xtal clock output i-r rbias i/o-u analog input/output defined in usb specification downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 13 usb5537b 4.0 standard interface connections 4.1 spi interface the hub will interface to external memory depending on confi guration of the usb5537b pins associated with each inter- face type. the usb5537b will first check to see whether an external spi flash is presen t. if not, the usb5537b will operate from internal rom. if spi flash is pres ent, the chip will operate from the external rom. the usb5537b is capable of code execution from an external spi rom. on power up, the fi rmware looks for an external spi flash device that contains a valid signature of 2dfu (device firmware upgrade) beginning at address 0xfffa. if a valid signature is found, then the ex ternal rom is enabled and the code exec ution begins at address 0x0000 in the external spi device. if a valid signature is not found, then execution continues from inter nal rom. the following sections describe the interface options to the external spi rom. 4.1.1 operation of the hi-speed read sequence the spi controller will automatically handl e code reads going out to the spi rom address. when the controller detects a read, the controller drops the spi_ce , and puts out a 0x0b, followed by the 24 -bit address. the spi controller then puts out a dummy byte. the next eight clocks clock in the firs t byte. when the first byte is clocked in a ready signal is sent back to the processor, and the processor gets one byte. after the processor gets the first byte, its address will change. if the address is one more t han the last address, the spi controller will clock out one more byte. if the address in anything other than one more th an the last address, the spi controller will terminate the transaction by taking spi_ce high. as long as the addre sses are sequential, the spi con- troller will keep clocking in data. figure 4-1: spi hi-speed read operation spi controller spi rom serial to parllel ce# clk si so usb hub address control cache spi_di downloaded from: http:/// usb5537b ds00001682c-page 14 ? 2012 - 2015 microchip technology inc. 4.1.2 operation of the dual hi-speed read sequence the spi controller also supports dual data mode (at 30 mh z spi speed only). when conf igured in dual mode, the spi controller will automatically handle reads going out to the spi rom. when the controller detects a read, the controller drops the spi_ce_n , and puts out a 0x3b, followed by the 24-bit ad dress. the spi controller then puts out a dummy byte. the next four clocks clock in the first byte. the data appears two bits at a time on data out and data in. when the first byte is clocked in a ready signal is sent ba ck to the processor, and the processor gets one byte. after the processor gets the first byte, the address will change. if the address is one more than the last address, the spi controller will clock out one more byte. if the address in anything other than one more th an the last address, the spi controller will terminate the transaction by taking spi_ce_n high. as long as the addresses are sequential, the spi con- troller will keep clocking in data. figure 4-2: spi hi-speed read sequence figure 4-3: spi dual hi-speed read operation spi_cen spi_clk spi_do spi_di 8 0b msb high impedance 15 16 123 4 05 7 6 d out add. 23 24 add. add. x 39 40 31 32 47 48 55 56 63 64 71 72 80 d out nn + 1 d out n+2 d out n+3 d out n+4 msb msb spi controller spi rom 2-serial to 8-parallel ce# clk si so address control cache spi_di usb hub downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 15 usb5537b 4.1.3 32-byte cache there is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. once the spi controller detects a jump, the base address pointer is initialized to that address. as each new sequential data byte is fetched, the data is written into the cache, and the length is in cremented. if the sequent ial run exceeds 32 bytes, the base address pointer is incremented to indicate the la st 32 bytes fetched. if the usb5537b does a jump, and the jump is in the cache address range, the fetch is done in 1 cl ock from the internal cache instead of an external access. 4.1.4 interface operatio n to spi port when not doing fast reads there is an 8-byte command buffer: spi_cmd_buf[7:0]; an 8-byte response buffer: spi _resp_buf[7:0]; and a length register that counts ou t the number of bytes: spi_cmd_len. ad ditionally, there is a self-clearing go bit in the spi_ctl register. once the go bit is set, the device drops spi_ce_n , and starts clocking. it will put out spi_cmd_len x 8 num- ber of clocks. after the first byte, the command, has been sent out, and the spi_di is stored in the spi_resp buffer. if the spi_cmd_len is longer than the spi_ cmd_buf, dont cares are sent out on the spi_do line. this mode is used for program execution out of internal ram or rom. figure 4-4: spi dual hi-speed read sequence figure 4-5: spi internally-controlled operation spi_cen spi_clk spi_do spi_di 8 0b msb high impedance 15 16 123 4 05 7 6 d1 add. 23 24 add. add. x 39 40 31 32 44 47 48 51 52 55 56 59 d2 nn + 1 d3 n+2 d4 n+3 d5 n+4 msb msb d1 d2 n n+1 d3 n+2 d4 n+3 d5 n+4 msb 43 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-7,5,3,1 bits-6,4,2,0 spi controller spi rom spi_rsp_buf[7:0] spi_cmd_buf[3:0] spi_cmd_len ce# clk si so usb hub downloaded from: http:/// usb5537b ds00001682c-page 16 ? 2012 - 2015 microchip technology inc. 4.1.4.1 erase example to perform a sctr_erase, 32blk_erase, or 64blk_erase, the device writes 0x20, 0x 52, or 0xd8, respectively to the first byte of the command buffer, followed by a 3-byte address. the length of the transf er is set to 4 bytes. to do this, the device first drops spi_ce_n , then counts out 8 clocks. it then puts out the 8 bits of command, followed by 24 bits of address of the location to be erased on the spi_do pin. when the transfer is complete, the spi_ce_n goes high, while the spi_di line is ignored in this example. 4.1.4.2 byte pr ogram example to perform a byte program, the device writes 0x02 to the firs t byte of the command buffer, followed by a 3-byte address of the location that will be written to, and one data byte. the l ength of the transfer is set to 5 bytes. the device first drop s spi_ce_n , 8 bits of command are clocked out, followed by 24 bits of address, and one byte of data on the spi_do pin. the spi_di line is not used in this example. figure 4-6: spi erase sequence figure 4-7: spi byte program spi_cen spi_clk 16 23 24 31 15 123 4 05 7 6 add. spi_do spi_di 8 command msb msb add. add. high impedance spi_cen spi_clk 16 23 24 31 15 39 123 4 05 7 6 0x00 spi_do spi_di 8 0xdb msb msb 0xfe /0xff data msb lsb 32 high impedance 0xbf downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 17 usb5537b 4.1.4.3 command only program example to perform a single byte command such as the following: - - wrdi -- wren - - ewsr - - chip_erase - - ebsy - - dbsy the device writes the opcode into the first byte of the spi_cmd_buf and the spi_cmd_len is set to one. the device first drops spi_ce , then 8 bits of the command are clocked out on the spi_do pin. the spi_di is not used in this exam- ple. 4.1.4.4 jedec-id read example to perform a jedec-id command, the device writes 0x9f into the first byte of the spi_cmd _buf and the length of the transfer is 4 bytes. the device first drops spi_ce_n , then 8 bits of the command are clocked out, followed by the 24 bits of dummy bytes (due to the length being set to 4) on the spi_do pin. when the transfer is complete, the spi_ce_n goes high. after the first byte, the data on spi_di is clocked into the spi_rsp_buf. at the end of the command, there are three valid bytes in the spi_rsp_buf. in this example, 0xbf, 0x25, 0x8e. figure 4-8: spi command only sequence spi_cen spi_clk 1234 05 7 6 spi_do spi_di command msb high impedance downloaded from: http:/// usb5537b ds00001682c-page 18 ? 2012 - 2015 microchip technology inc. 4.2 smbus slave interface next, the usb5537b will look to receive configuration and co mmands from an optional smbus master (if present). when smbus is enabled, the smbus can operate in either legacy (usb 2.0 only) or advanced mode (access to both usb 2.0 and 3.0 registers). next, the usb5537b will look for (optiona l) configuration present in the internal otp memory. any register settings that are modified via the smbus interface will overwrite the internal otp settings. the smbus slave interface is enabled when pull-up resistors are detected on both sm_dat and sm_clk for the first millisecond after reset. for operation in smbus legacy m ode, an additional pull-up resistor is required on trst . if the smbus interface is enabled, then the usb5537b will wait i ndefinitely for the smbus host to configure the device. once smbus configuration is complete, device initialization will proceed. to disable the smbus, a pull-down resistor of 10 k ? must be applied to either sm_dat , sm_clk , or both sm_dat and sm_clk if desired. if smbus is disabled, the device proceeds directly to device initia lization using the internal otp rom. 4.2.1 pull-up resistor for smbus external pull-up resistors (10 k ? recommended) are required on the sm_dat and sm_clk pins when implementing either smbus mode. figure 4-9: spi jedec-id sequence spi_cen spi_clk spi_do spi_di 8 9f msb high impedance 11 12 13 14 15 16 123 4 05 7 6 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 bf 25 8e msb msb downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 19 usb5537b 4.2.1.1 invalid protocol response behavior note that any attempt to update register s with an invalid protocol will not be updat ed. the only valid protocols are write block and read block (described section 5.5, "smbus slave interface," on page 29 ), where the hub only responds to the 7-bit hardware selected slave addresses (0101100b or 01011 01b). additionally, the only valid registers for the hub are outlined in the usb5537b configuration release notes documentation. 4.2.2 slave device timeout devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25 ms (t timeout, min ). the master must detect this condition and gener ate a stop condition within or after the transfer of the interrupted data byte. slave devices must reset th eir communication and be able to receive a new start condi- tion no later than 35 ms (t timeout, max ). 4.2.3 stretching the sclk signal the hub supports stretching of the sclk by other devices on the smbus. the hub will stretch the clock as needed. 4.2.4 bus reset sequence the smbus slave interface resets and returns to the idle state upon a start condition followed immediately by a stop condition. 4.2.5 smbus alert response address the smbalert# signal is not supported by the usb5537b. figure 4-10: smbus slave connection note: some simple devices do not contain a clock low drive circ uit; this simple kind of de vice typically resets its communications port after a start or stop condition. the slave device timeout must be implemented. master sm_clk sm_dat scl sda vdd 10 k ? usb hub 10 k ? downloaded from: http:/// usb5537b ds00001682c-page 20 ? 2012 - 2015 microchip technology inc. 4.3 reset there are two different resets that the device experiences. o ne is a hardware reset (either from the internal por reset circuit or via the reset_n pin) and the second is a usb bus reset. 4.3.1 internal por all reset timing parameters are guaranteed by design. 4.3.2 external hardware reset a valid hardware reset is defined as assertion of reset_n for a minimum of 1 ? s after all power supplies are within operating range. assertion of reset_n (external pin) causes the following: 1. the phy is disabled, and the differentia l pairs will be in a high-impedance state. 2. all transactions immediately te rminate; no states are saved. 3. all internal registers return to the default state. 4. the external crystal oscillator is halted. 5. the pll is halted. 4.4 standard port power configuration the device natively operates with standar d port power controllers or poly-fuse devices for the downstream port powers when battery charging is not enabled on a port. it is not recommended to have the downstream ports of a single device mix poly-fuse and standard power controller support, as the co nfiguration of the hub cannot correctly report which ports are poly-fuse and which are port power controllers to the host. any port without battery charging can also be used in indi vidual port power controls or ganged power controls. the port power control output only supports either ganged or indivi dual modes on a global basis for all downstream ports. the overcurrent setting also supports individual or global setti ngs, but also adds the ability to configure specific ports to be part of an overcurrent gang with others setup for indivi dual connections. this hybrid configuration should only be used when utilizing poly-fuse power devices. 4.4.1 port power controller the most common method for downstream port power controls is to utilize curren t-limited power switches for usb appli- cations. the devices allow the downstream port powers to be enabled through a control si gnal and report over-current conditions through a flag output. two connection methods are possible for these controllers, combined mode and independent mode. in combined mode, the flg and en signals are tied togethe r with an external 10k ohm pull-up and driven to a single prt_ctl signal on the device, as shown in figure 4-11 . downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 21 usb5537b in individual mode, the prt_ctl signal is driven directly to the en input of the power s witch and the ocs input is con- nected to the flg output of t he power switch with a 10k pull-up connected, as shown in figure 4-12 . figure 4-11: combined mode implementation figure 4-12: individual mode implementation note: ports 1-4 have the option to be configured for either co mbined mode or individual mode, but ports 5-7 only support combined mode connections. usb power switch en ocs 5v usb device prt_ctl usb553x usb power switch en 5v usb device prt_ctl flg ocs usb553x 10k 5v downloaded from: http:/// usb5537b ds00001682c-page 22 ? 2012 - 2015 microchip technology inc. 4.4.2 poly-fuse an alternate method of downstream power control is to utiliz e poly-fuse devices. in this configuration, the poly-fuse devices are used to report overcurrent conditions to the usb5537b through the ocs input, as shown in figure 4-13 . 4.5 charging port configurations the device can also be configured to operate as a charging port for one or more downstream ports. ganged port power control and/or overcurrent is not supported if any of the downstream ports ar e configured as charging ports. if a port is configured to support a charging port mode, either a standard port power c ontroller or a ucs1002 may be implemented. for more information on charging port support, refer to section 5.1, "charging port configuration," on page 24 . 4.5.1 port power controller the only special limitation of using the de vice as a charging port is that the port power controller must be capable of the higher current to support the charging port modes. refer to section 4.4.1, "port power controller," on page 20 for more information on this implementation. 4.5.2 ucs1002 using a ucs1002 device as a downstream port power controller is only supported on ports that are enabled as charging ports. if the ucs1002 is implement ed, the usb5537b communicates with all of the implemented ucs100 2 ports over smbus using one of the prt_ctlx/ocsx signals as the smclk/ smdat. additionally, dyncpdis_n becomes the ucs_sm- balert_n signal. multiple ucs1002 devices may be connected to the smbus in parallel. after reset, for any enabled charging ports, the u sb5537b performs smbus commands on the configured prt_ctlx/ocsx signals and checks ucs1002 devices at specific addresses (see ta b l e 4 - 1 ) to confirm which ports are utilizing ucs1002 devices as t he downstream power controllers. figure 4-13: poly-fuse implementation ocs usb device 5v poly fuse usb553x 10k 3.3v downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 23 usb5537b in this configuration, the ucs1002 is utilized as an smbus enabled port power switch and all charging port handshaking on the d+/d- signals are controlled directly from th e usb5537b. an example implementation can be seen in figure 4- 14 . table 4-1: ucs1002 address mapping port address 1 0x30 2 0x31 3 0x32 4 0x33 5 0x34 6 0x35 7 0x36 figure 4-14: ucs1002 charging implementation d- 5v usb553x d+ usb2dm_dn1 usb2dp_dn1 ssrx- ssrx+ usb3dm_rxdn1 usb3dp_rxdn1 sstx-sstx+ usb3dm_txdn1 usb3dp_txdn1 0.1uf 0.1uf gnd1 gnd2 vbus 100uf shl1 shl2 shr1shr2 0.1uf shield port 1 usb 3 a-type receptacle 330 vbus1vbus2 smclk/s0 smdata/latch alert dpin m1m2 ucs1002 prt_ctl1 dmin dpout dmout em_en comm_sel sel 47k 33k 10k trst/dyncpdis_n/ ucs_smbalert_n 3.3v 10k 10k tck/ocs1 downloaded from: http:/// usb5537b ds00001682c-page 24 ? 2012 - 2015 microchip technology inc. 5.0 functional operation this chapter details the functional operation of various device features. 5.1 charging port configuration the usb5537b supports downstream charging ports on any available port. the hub contains internal hardware and algorithms to natively support various voltage levels on t he d+/d- signals along with the bc 1.2 handshaking protocol, allowing charging devices to detect the downstream port as a charging port. a port can be configured for either rapidcharge suppor t or samsung legacy charging mode support. this section details the various charging port modes. the following terminology will be helpful in the understanding of these features: sdp - standard downstream port - a port that is no t operating as a charging port and has active usb communi- cations. cdp - charging downstream port - a port that is oper ating as a charging port and has active usb communica- tions. dcp - dedicated charging port - a port that is oper ating as a charging port but has no usb communications. s0 - normal system power state in full run. s3 - typically a sleep state, where the system can be woken from usb hid devices s4 - typically a hibernate sleep state, where the system state is stored to a hard drive an d does not support wake from usb hid devices. s5 - typically an off state for a system. 5.1.1 rapid charge this mode enables concurrent operation of apple, bc 1. 2 and dp/dm shorted emulation charging. the only applicable options are to choose apple 1a or apple 2a charging mode on a per port basis. refer to section 5.2.1.1, "apple charging mode," on page 26 . 5.1.2 samsung legacy charging this mode drives a specified voltage on the dp/dm lines to allow legacy samsung devices to detect the port as charging capable. this is only operational in dcp modes. 5.1.3 dynamic charging port (6070 and 6080 only) dynamic charging port support utilizes the devices dy ncpdis_n pin to disable battery charging support globally when low and, when high, allow any ports configured as charging ports (either through a conf iguration file or straps) to resume their battery charging operat ion in the configured charging mode. this feature is currently supported only when using standard usb port power controllers. please contact your microchip fae if required to use this feature with other port power controller configurations. figure 5-1 , figure 5-2 , and figure 5-3 detail the operation of dynamic chargi ng port in the s0, s3, and s4/s5 power modes, respectively. for any of the flow diag ram transitions, there is a y/z nomenclature. y = dynamic bc enable signal z = device attached and sensed by device note: apple and dp/dm shorted emulation charging modes are only operational in dcp mode. note: the dynamic charging port feature and related dyncpdi s_n pin function is available in the -6070 and -6080 versions of the device only. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 25 usb5537b figure 5-1: s0 state transitions figure 5-2: s3 state transitions figure 5-3: s4/s5 state transitions cdp dcp sdp 1/x s0 1/0 0/x 1/1 0/1 0/0 cdp dcp sdp x/0 0/x 1/x x/1 s3 power ? cycle x/x 1/x power ? cycle x/x 0/x cdp dcp sdp x/x 0/x 1/x s4/s5 power ? off x/x power ? cycle x/x power ? on 1/x 0/x downloaded from: http:/// usb5537b ds00001682c-page 26 ? 2012 - 2015 microchip technology inc. 5.2 configuration options by default, the usb5537b configuration allows the device to operate as a standard usb hub when connected to a usb host controller. the device also contains a number of config urable options which can be se t through its user interfaces: one-time programmable (otp) memory (one time burn configuration) external spi (only when using external spi firmware) smbus slave interface (controlled by smbus host controller. must be updated every time.) refer to standard interface connections on page 13 for details on the spi and smbus interfaces. spi and otp configuration can be created and applied thro ugh the protouch tool. the following subsections detail to various device parameters that can be configured via the protouch tool. 5.2.1 charging port enable this option enables, on a per-port basis, dfps to become charging ports. if this is enabled on a port, it must be config- ured as a per-port pwr/ocs control. ganged ocs or pwr controls are not su pported concurrently. the normal con- figuration is to support the rapidcharge protocol. refer to section 5.2.17, "port powe r/ocs control," on page 27 for more information. 5.2.1.1 apple charging mode this option enables either apple 1 amp or apple 2 amp for the rapidcharge protocol charging mode when a port is configured as a charging port and not enabled for sams ung mode. this mode enables the selected apple charging mode to operate concurrently with bc1.2. 5.2.1.2 samsung charging mode this option enables the samsung charging mode on a port. if this is selected, the apple charging mode setting is ignored and only the samsung charging mode is supported on that port. 5.2.1.3 ucs1002 smbus interface selection usc1002 port power controllers are only supported if battery charging is enabled on that port. when bc is enabled, there is an option to select the extern al signals (prtctlx/ocsx) that are used for the smbus sda/scl signals. only ports 1-4 signals can be used. this feature is supported on the -6070, -6080 and newer devices. 5.2.2 usb vid this field is the 16-bit usb vendor id reported by both usb 2.0 and usb 3.0 hubs. 5.2.3 usb2 pid this field is the 16-bit usb product id reported by the usb 2.0 hub only. 5.2.4 usb3 pid this field is the 16-bit usb product id reported by the usb 3.0 hub only. 5.2.5 usb did this field is the 16-bit usb device id re ported by both the usb 2.0 and usb 3.0 hubs. 5.2.6 usb non-re movable setting this is the per-port non-removable setting for both usb 2. 0 and usb 3.0 hubs. if any ports are set as non-removable, both the usb 2.0 and usb 3.0 hubs will be automatically set to report as compound devices. 5.2.7 usb port disables this is the per-port setting used to disable ports for both usb 2.0 and usb 3.0 hubs. 5.2.8 usb self/bus-powered this setting is used to configure the usb2 and usb3 hubs to report as self-powered or bus-powered. 5.2.9 usb system max power this field is the maximum total system power on vbus including non-removable devices if permanently attached. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 27 usb5537b 5.2.10 usb hub max current this field is the maximum current of the hub and system components to support the hub on vbus. 5.2.11 usb language id this field selects the usb language id. 5.2.12 usb manufacturer string this field contains the manufacturer string reported by both usb 2.0 and us b 3.0 hubs (maximum of 30 characters). 5.2.13 usb 2.0 product string this field contains the product string reported by the usb 2.0 hub (maximum of 30 characters). 5.2.14 usb 3.0 product string this field contains the product string reported by the usb 3.0 hub (maximum of 30 characters). 5.2.15 usb serial string this field contains the serial string reported by the usb 2.0 and usb 3.0 hubs (maximum of 30 characters). 5.2.16 pin strap disables this setting disables the external pin configuration st raps on power-up that select the following on ports 1-4: port disable port non-removable battery charging enable if the user needs to select the above sett ings in a configuration file for ports 1- 4, they must also disable the pin straps to ensure the settings are not overridden by the strap controls. 5.2.17 port powe r/ocs control 5.2.17.1 per-port pwr/ocs combined mode this per-port setting controls whether the power enable and ocs signals are on the same pin. this setting is only valid for ports 1-4. ports 5-7 can only operate in combi ned mode or ganged mode due to pin configurations. refer to section 4.4, "standard port power configuration," on page 20 for additional port power setting details and con- nection diagrams. 5.2.17.2 ocs gang control this setting can gang multiple ports into an ocs ganging to report overcurrent on any port in this gang. all ganged this single setting configures all ports into an ocs gang. split ganged this setting allows the user to gang sele ct ports together while not ganging others. requires the setting of the following: usb 2.0 hub ocs gang set usb 3.0 hub ocs gang set ports contained within the ocs gang (any other por ts will operate as a per-port power control/ocs) gpio used as ocs gang input 5.2.17.3 usb port power gang control this setting can gang all ports into single port power control. downloaded from: http:/// usb5537b ds00001682c-page 28 ? 2012 - 2015 microchip technology inc. 5.2.17.4 no port power controls this parameter requires setting the hubs power-on time to 0 for both usb 2.0 and usb 3.0 hubs. it also requires the setting of the usb3 pwr_sw_ctl signal. usb power-on time (advanced) this parameter sets the usb power-on to power good time in 2ms intervals for both the usb 2.0 and usb 3.0 hubs. usb 3.0 no power switch select when enabled, the usb 3.0 hub operates in accordance wi th the usb 3.0 specification for no power switches. 5.2.17.5 usb 2.0 over-current timer this setting controls the signal filter on the ocs pin for the usb 2.0 hub. these settings should be controlled with care, as the default configuration has been tested thoroughly. the valid settings are: 50ns 1000ns 200ns 400ns 5.2.17.6 usb 3.0 over-current timer this setting controls the signal filter on the ocs pin for the usb 3.0 hub. these settings should be controlled with care, as the default configuration has been tested thoroughly. the valid settings are: 750ns 10000ns 1250ns 1500ns 5.2.18 usb2 port dp/dm pin swap this per-port setting internally swaps the dp and dm signals for the usb 2.0 port. port 0 = ufp port 1-7 = dfp ports 1-7 5.2.19 usb 2.0 port hs output current this per-port setting boosts t he usb high-speed driver output. port 0 = ufp port 1-7 = dfp ports 1-7 settings are defined wit hin the protouch tool. 5.2.20 usb 2.0 port squelch this per-port setting modifies the usb input squelch setting. port 0 = ufp port 1-7 = dfp ports 1-7 settings are defined wit hin the protouch tool. 5.2.21 usb 2.0 hub advanced controls the settings in the following sub-sections are advanced contro ls, which most applications will not require to be set, since the default configurations allow seamless operation. only advanced users/applications should override the default con- figurations detailed here. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 29 usb5537b 5.2.21.1 usb 2.0 hs disable this setting disables usb high-spee d operation on the entire usb 2.0 hub. 5.2.21.2 usb 2.0 mtt disable this setting disables the multi-tt operation on the entire usb 2.0 hub. 5.2.21.3 usb 2.0 fs eop disable this setting disables the end of packet (eop) generation of end of frame 1 (eof1) when in full-speed mode. 5.2.22 uuid override these controls allow the user to overri de the 128-bit uuid value within the devic e (set at the microchip factory as a unique value for each device). by usb specification, if mu ltiple devices are connected within one system as a single compound device, all uuid (within the bos descriptor) should be set the same. 5.3 one-time programmable (otp) memory the device contains an internal one-time programmable me mory, which allows various configuration settings to be configured for the end application. this memory requires a configuration to be created through the microchip protouch tool or by a microchip fae. the protouch tool then allo ws programming of this block over a usb 2.0 connection to a microsoft windows host. there is also an option to support otp programming via th e smbus interface. however, this method of otp program- ming is not preferred. please contact your local microchi p fae for more information on otp programming via smbus. 5.3.1 configuration file creation for information on configur ation file creation, refer to the protouch tool. 5.4 external spi the device supports operation utilizing an external spi flash or rom. in normal o peration, the inter nal microcontroller runs from the internal rom. if an external spi memory is implemented, the full firmware image must be loaded into the spi. when using an external spi memory, there are two options av ailable. the configuration ca n be loaded from the internal otp, or the internal otp can be ignored and t he configuration file loaded into the spi memory. please contact your microchip fae for more information on how to obtain access to an external spi memory image and how to support the different configuration options. for information on spi interface connections, refer to section 4.1, "spi interface," on page 13 . 5.4.1 configuration file creation for information on configur ation file creation, refer to the protouch tool. 5.5 smbus slave interface typical block write and block read protocols are shown in figure 5-6 and figure 5-5 . smbus ram buffer offset accesses are performed using 7-bit slave addressi ng, a 16-bit smbus ram buffer offset field (for legacy and advanced modes, respectively), and an 8-bit data field. the shading shown in the figures during a read or writ e indicates the hub is driving data on the sm_dat line; otherwise, host data is on the sm_dat line. the smbus slave address assigned to the hub (0101100b or 0101101b) allows it to be identified on the smbus. the smbus ram buffer offset field is the internal offset in smbus ram to be accessed. the data field is the data that the host is attempting to read/write from/to the smbus ram buffer. for information on connecting the smbus slave interface to a host, refer to section 4.2, "smbus slave interface," on page 18 . note: data bytes are transferred msb first. downloaded from: http:/// usb5537b ds00001682c-page 30 ? 2012 - 2015 microchip technology inc. 5.5.1 block write the block write begins with a slave addre ss and a write condition. after the comm and code, the host issues a byte count which describes how many more bytes will follow in the message. if a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count may not be zero. a block write or read allows a transfer maximum of 32 data bytes. for the following smbus tables: figure 5-4: block write 5.5.2 block read a block read differs from a block write in that the repeated start condition exists to satisfy the i 2 c specifications require- ment for a change in the transfer direction. figure 5-5: block read 5.5.3 standard smbus commands there are special commands that can be sent in the place of the 16-bit address bytes. these commands are used to enumerate the hub, access the configurat ion registers, or simply reset the de vice. the commands consist of the 16-bit command followed by a 00h byte to terminate the command. figure 5-6: smbus commands denotes master-to-slave denotes slave-to-master s slave address smbus ram buffer offset wr a 171 11 6 a 1 ... 1 81 byte count = n a data byte 1 a data byte 2 a 81 1 1 88 data byte n a p 1 s s slave address smbus ram buffer offset wr 171 1 1 6 a 1 slave address rd a 71 1 ... a 81 1 1 88 1 81 p a a a a byte count = n data byte 2 data byte 1 data byte n s slave address opcode wr a 171 11 6 a 1 ... downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 31 usb5537b 5.5.4 special hub commands below is a list of the extended command s and the code used to execute them. the extended commands provide access to the status of the device. from these registers a smbus controller can see the connection status of the hub, communicate with t he ucs1000, and change the smbus address if desired. when the extended command is sent the hub will interpret the memory starting at offset 00h as follows: table 5-1: special smbus commands operation opcode description reboot 9936h reboot internal mcu. configuration register access 9937h read and write configuration registers extended command 993eh execute extended status commands usb attach aa55h enter configuration stage usb attach with smbus access aa56h enter configuration stage with smbus access enabled table 5-2: extended commands command code set address 00h get default address 01h get hub info 02h get ucs port mask 03h port connect status 80h port power status 81h port force disable 82h port dp/dm status 83h ucs byte read 84h ucs byte write 85h ucs block read 86h ucs block write 87h table 5-3: memory format for extended hub command ram address description notes 0000h command code of the extended command to execute. 0001h status always write 0 to this register, it will be updated after the command is exe- cuted with the status. 0002h data1 the first byte of data to write to or read from when executing the command. ... ... ... 0004h+n datan the nth byte of data to write to or read from when executing the command. downloaded from: http:/// usb5537b ds00001682c-page 32 ? 2012 - 2015 microchip technology inc. 5.5.4.1 special command example the following example shows how to read the charger detecti on register to find out what type of charger the hub has connected to: 1. first write data to the memory of the hub . 2. after the data is written, execute the configuration register access command . 3. finally, read back data starting at memory offs et 04h, which is where the data byte starts . although the device can send out 128 bytes of memory data, it isnt necessary to read the entire set, the smbus master can send a stop at any time. table 5-4: example smbus write command byte value comment 0 5ah address plus write bit. 1 00h memory address 00 00h. 2 00h memory address 00 00 h. 3 03h number of bytes to write to memory. 4 80h get port device status. 5 00h reading one data bytes. 6 1fh read all ports. table 5-5: configuration register access command byte value comment 0 5ah address plus write bit. 1 99h command 99 3eh. 2 3eh command 99 3e h. 3 00h command completion. table 5-6: example smbus read command byte value comments 0 5ah address plus write bit. 1 00h memory address 00 04h. 2 03h memory address 00 04 h. 0 59h address plus read bit. 1 80h device sends 128 bytes of data. 2 03h upstream connection status. (ss and hs) 3 02h port 1 connection status. (hs/fs/ls only) 4 01h port 2 connection status. (ss only) 5 02h port 3 connection status.(hs/fs/ls only) 6 02h port 4 connection status.(hs/fs/ls only) downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 33 usb5537b 5.5.4.2 set address (00h) the set address command will change the smbus address to the value in data1 or memory address 0002h. the next smbus read will have to account for this change in address. 5.5.4.3 get default address (01h) this command will always return the default address of the usb5x3xb (2dh). 5.5.4.4 get hub info (02h) the command will return the status of the hub in da ta1. the status byte follows the following format: 5.5.4.5 get ucs port mask(03h) this will return a mask of which port is assigned a ucs port controller based on the ucs device detection. 5.5.4.6 port connect status (80h) data1 of the memory is written by the smbus master and after the command is executed data 2-6 will be populated with the status of each port. data1 is a port mask where each bit represents the port status to return. bit 0 is the upstream port, bit 1 is the down- stream port 1, etc. the port connect status byte can be interpreted as follows: table 5-7: set address byte set addr (0 x 00) smbus address bit name r/w description 7 default w resets to the default smbus address. 7:0 address w new smbus address table 5-8: hub information usb2_hub_info (0 x 02) usb2 hub information bit name r/w description 7 configured r 1 = hub is in the configured state. 2 = hub is in the unconfigured state. 6:0 usb2_address r the address of the usb2 hub. table 5-9: hub information port_connect (0 x 80) port connect status bit name r/w description 7:6 reserved r reserved 5 usb2_suspend r 0 = port is not suspended. 1 = port is in the l2 suspend state. 4 usb3_suspend r 0 = port is not suspended. 1 = port is in the u3 suspend state. 3:2 reserved r reserved downloaded from: http:/// usb5537b ds00001682c-page 34 ? 2012 - 2015 microchip technology inc. 5.5.4.7 port power status (81h) data1 of the memory is written by the smbus master and after the command is executed data 2-6 will be populated with the status of each port. a 1 means the port powe r is enabled, a 0 means the port power is disabled. data1 is a port mask where each bit represents the port status to return. bit 0 is the upstream port, bit 1 is the down- stream port 1, etc. 5.5.4.8 port force disable (82h) data1 of the memory is the port mask and data 2-6 is the port disable state requested. data1 is a port mask where each bit represents the port status to return. bit 0 is the upstream port, bit 1 is the down- stream port 1, etc. the port disable byte will be interpreted as follows: 5.5.4.9 port dp/dm status (83h) data1 of the memory is written by the smbus master and after the command is executed data 2-6 will be populated with the status of each port. data1 is a port mask where each bit represents the port status to return. bit 0 is the upstream port, bit 1 is the down- stream port 1, etc. the port dp/dm status byte can be interpreted as follows: 1 usb2_connect r 0 = no usb2 connection detected. (hs/fs/ls) 1 = usb2 connection detected. 0 usb3_connect r 0 = no usb3 connection detected. 1 = usb3 connection detected. table 5-10: hub information port_disable (0 x 82) port disable bit name r/w description 7 overwrite w if this bit is 1 then the data in bits 2:0 will be overwritten. 6:3 reserved w reserved 2 force_off w 0 = port power controlled by hub. 1 = port power forced off. 1 usb3_term_dis w 0 = usb3 term inations controlled by hub. 1 = usb3 terminations disabled. 0 usb2_term_dis w 0 = usb2 term inations controlled by hub. 1 = usb2 terminations disabled. table 5-11: port dp/dm status port_dpdm (0 x 83) port dp/dm status bit name r/w description 7:2 reserved w reserved 1 fs_dm w 0 = dm line is below the fs threshold. 1 = dm line is above the fs threshold (ls idle state) 0 fs_dp w 0 = dp line is below the fs threshold. 1 = dp line is above the fs threshold. (fs idle state) table 5-9: hub information (continued) port_connect (0 x 80) port connect status bit name r/w description downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 35 usb5537b 5.5.4.10 ucs byte read (84h) the first data byte (data1) contains the address of the ucs register to read. the second data byte (data2) will contain the data after the command is executed. 5.5.4.11 ucs byte write (85h) the first data byte (data1) contains the address of the ucs register to write to. the second data byte (data2) contains the data to be written. 5.5.4.12 ucs block read (86h) the first data byte (data1) contains the address of the ucs re gister to read. the second data byte (data2) contains the number of bytes to read. the subsequent data bytes will be p opulated with the contents of the data2 registers starting at data1. 5.5.4.13 ucs block write (87h) the first data byte (data1) contains the address of the ucs register to write to. the second data byte (data2) contains the number of bytes to write. the subsequent data bytes contain the data to write. 5.6 runtime register definitions below is the list of configuration registers and their address . the init column contains the values that will be loaded when the usb attach commands are sent. register definiti ons are provided in the subseq uent sub-sections. for infor- mation on accessing these registers, refer to section 5.6.1, "accessing ru ntime registers," on page 37 . table 5-12: configuration register memory map addr r/w name function init 0806h r/w led0_pio0_ctl1 led0/pio0 register 1 00h 0807h r/w led0_pio0_ctl2 led0/pio0 register 2 00h 0808h r/w led1_pio1_ctl1 led1/pio1 register 1 00h 0809h r/w led1_pio1_ctl2 led1/pio1 register 2 00h 082dh r/w vbus_ocs_pd vbus and ocs pull-down register 00h 082fh r/w led0_pd led0 pull-down register 00h 0831h r/w vbus_ocs_dir vbus and ocs direction register 00h 0833h r/w led0_dir led0 direction register 00h 0835h r/w vbus_ocs_out vbus and ocs output register 00h 0837h r/w led0_out led0 output register 00h 0839h r/w vbus_ocs_in vbus and ocs input register note 5-1 083bh r/w led0_in led0 input register note 5-1 083dh r/w vbus_ocs_pu vbus and ocs pull-up resistor register feh 083fh r/w led0_pu led0 pull-up resistor register 00h 092eh r/w prt_pwr_pd port power pull-down resistor register 00h 0932h r/w prt_pwr_dir port power direction register 00h 0936h r/w prt_pwr_out port power output register 00h 093ah r/w prt_pwr_in port power input register note 5-1 downloaded from: http:/// usb5537b ds00001682c-page 36 ? 2012 - 2015 microchip technology inc. 093eh r/w prt_pwr_pu port power pull-up resistor register 00h 3c00h r/w prt_pwr_sel1 port 1 power se lect register 03h 3c04h r/w prt_pwr_sel2 port 2 power se lect register 03h 3c08h r/w prt_pwr_sel3 port 3 power se lect register 03h 3c0ch r/w prt_pwr_sel4 port 4 power se lect register 03h 3c10h r/w prt_pwr_sel5 port 5 power se lect register 24h 3c14h r/w prt_pwr_sel6 port 6 power se lect register 23h 3c18h r/w prt_pwr_sel7 port 7 power se lect register 23h 3c20h r/w ocs_cfg_sel1 port 1 ocs select register 01h 3c24h r/w ocs_cfg_sel2 port 2 ocs select register 01h 3c28h r/w ocs_cfg_sel3 port 3 ocs select register 01h 3c2ch r/w ocs_cfg_sel4 port 4 ocs select register 01h 3c30h r/w ocs_cfg_sel5 port 5 ocs select register 01h 3c34h r/w ocs_cfg_sel6 port 6 ocs select register 01h 3c38h r/w ocs_cfg_sel7 port 7 ocs select register 01h 5246h r/w cdp_detect charging downstream detected register note 5-1 525ah r/w osc_gang ocs gang control register 00h 525bh r/w ocs_gang_gpio ocs gang signal select register 00h 60cah r/w hs_up_boost usb upstream boost register 00h 60cch r/w hs_up_sense usb upstream varisense register 00h 61c0h r/w ss_up_state usb3 upstream link state register note 5-1 64cah r/w hs_p1_boost usb port 1 boost register 00h 64cch r/w hs_p1_sense usb port 1 varisense register 00h 65c0h r/w ss_p1_state usb3 port 1 link state note 5-1 68cah r/w hs_p2_boost usb port 2 boost register 00h 68cch r/w hs_p2_sense usb port 2 varisense register 00h 69c0h r/w ss_p2_state usb3 port 2 link state note 5-1 6ccah r/w hs_p3_boost usb port 3 boost register 00h 6ccch r/w hs_p3_sense usb port 3 varisense register 00h 6dc0h r/w ss_p3_state usb3 port 3 link state note 5-1 70cah r/w hs_p4_boost usb port 4 boost register 00h table 5-12: configuration register memory map (continued) addr r/w name function init downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 37 usb5537b note 5-1 status registers do not have a default value because the status can change depending on system conditions. 5.6.1 accessing runtime registers the configuration register access operation allows the smbus master to read or write to t he internal registers of the hub. when the configuration register a ccess command is sent the hub will interpret the memory starting at offset 00h as follows: 5.6.1.1 configuration register write example the following example shows how the smbus messages will be fo rmatted to set the vid of the hub to a custom value, aa55h. 1. write data to the memory of the hub: 70cch r/w hs_p4_sense usb port 4 varisense register 00h 71c0h r/w ss_p4_state usb3 port 4 link state register note 5-1 74cah r/w hs_p5_boost usb port 5 boost register 00h 74cch r/w hs_p5_sense usb port 5 varisense register 00h 78cah r/w hs_p6_boost usb port 6 boost register 00h 78cch r/w hs_p6_sense usb port 6 varisense register 00h 7ccah r/w hs_p7_boost usb port 7 boost register 00h 7ccch r/w hs_p7_sense usb port 7 varisense register 00h table 5-13: memory format for configuration register access ram address description notes 0000h direction 0 = register write, 1 = register read. 0001h data length number of bytes to read/write when executing the command. 0002h configuration address msb the upper byte of the 16-bit configuration register address. 0003h configuration address lsb the lower byte of the 16-bit configuration register address. 0004h data1 the first byte of data to write to or read from the configuration address. ... ... ... 0004h+n datan the nth byte of data to write to or read from the configuration address, n is equal to the data length. table 5-14: example smbus write command byte value comment 0 5ah address plus write bit. 1 00h memory address 00 00h. 2 00h memory address 00 00 h. 3 06h number of bytes to write to memory. 4 00h write configuration register. 5 02h writing two data bytes. 6 30h vid is in register 30 00h. 7 00h vid is in register 30 00 h. table 5-12: configuration regi ster memory map (continued) addr r/w name function init downloaded from: http:/// usb5537b ds00001682c-page 38 ? 2012 - 2015 microchip technology inc. 2. execute the configurati on register access command: 5.6.1.2 configuration register read example the following example shows how to read the charger detecti on register to find out what type of charger the hub has connected to: 1. write data to the memory of the hub. 2. execute the configurati on register access command. 3. read back data starting at memory offset 04h, which is where the data byte starts. 8 55h lsb of vendor id aa 55 h. 9 aah msb of vendor id aa 55h. table 5-15: configuration register access command byte value comment 0 5ah address plus write bit. 1 99h command 99 37h. 2 37h command 99 37 h. 3 00h command completion. table 5-16: example smbus write command byte value comment 0 5ah address plus write bit. 1 00h memory address 00 00h. 2 00h memory address 00 00 h. 3 04h number of bytes to write to memory. 4 01h read configuration register. 5 01h reading one data bytes. 6 30h bc detect is in register 30 e2h. 7 e2h bc detect is in register 30 e2 h. table 5-17: configuration register access command byte value comment 0 5ah address plus write bit. 1 99h command 99 37h. 2 37h command 99 37 h. 3 00h command completion. table 5-18: example smbus read command byte value comments 0 5ah address plus write bit. 1 00h memory address 00 04h. 2 04h memory address 00 04 h. 3 59h address plus read bit. 4 80h device sends 128 bytes of data. 5 56h charging downstream port detected. table 5-14: example smbus write command (continued) byte value comment downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 39 usb5537b although the device can send out 128 bytes of memory data, it isnt necessary to read the entire set, the smbus master can send a stop at any time. 5.6.2 led0/pio0 register 1 5.6.3 led0/pio0 register 2 table 5-19: led0/pio0 register 1 led0_ctl1 (0 x 0806) led0_pio0 control register bit name r/w description 7 xnor r/w this bit toggles the polarity of th e led output. it can be used to invert the polarity. 6 mode r/w 0 - blink the led. 1 - breath the led. 5:0 rate r/w in blink mode: this is the blink rate of led in 50 ms increments. duty cycle of 50%. rate range is 50 ms to 3.15 seconds. in breath mode: this is the time for an active breadth in 500 ms increments. table 5-20: led0/pio0 register 2 led0_ctl2 (0 x 0807) led0_pio0 control register 2 bit name r/w description 7:2 trailoff_time r/w in blink mode: time the le d must continue blinking after led_on is turned off. trail_time is in 50ms increments. range is 50 ms to 3.15 seconds. in breath mode: this is the time for an sleeping in between breadths in 500 ms increments 1 led_on r/w if led_on is set, then st art blinking or breathing this led. blink timer starts when this bit is enabled. no short blinks permitted. when this bit is disabled, blinking stops when trail_time expires. in breath mode: breath timer starts when this bit is enabled. no short blinks permitted. when this bit is disabled, blinking stops immediately. 0 led_pio r/w 0 = pio0 1 = led0 downloaded from: http:/// usb5537b ds00001682c-page 40 ? 2012 - 2015 microchip technology inc. 5.6.4 led1/pio1 register 1 5.6.5 led1/pio1 register 2 table 5-21: led1/pio1 register 1 led1_ctl1 (0 x 0808) led1_pio1 control register bit name r/w description 7 xnor r/w this bit toggles the polarity of the led output. it can be used to invert the polarity. 6 mode r/w 0 - blink the led. 1 - breath the led. 5:0 rate r/w in blink mode: this is the blink rate of led in 50 ms increments. duty cycle of 50%. rate range is 50 ms to 3.15 seconds. in breath mode: this is the time for an active breadth in 500 ms increments. table 5-22: led1/pio1 register 2 led1_ctl2 (0 x 0809) led1_pio1 control register bit name r/w description 7:2 trailoff_time r/w in blink mo de: time the led must continue blinking after led_on is turned off. trail_time is in 50ms increments. range is 50 ms to 3.15 seconds. in breath mode: this is the time for an sleeping in between breadths in 500 ms increments. 1 led_on r/w if led_on is set, then start blinking or breathing this led. blink timer starts when this bit is enabled. no short blinks permitted. when this bit is disabled, blinking stops when trail_time expires. in breath mode: breath timer starts when this bit is enabled. no short blinks permitted. when this bit is disabled, blinking stops immediately. 0 led_gpio r/w 0 = pio1 1 = led1 downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 41 usb5537b 5.6.6 vbus and ocs pull-down register 5.6.7 led0 pull-down register 5.6.8 vbus and ocs direction register table 5-23: vbus and ocs pull-down register vbus_ocs_pd (0 x 082d) vbus and ocs pull-down register bit name r/w description 7:5 reserved r/w reserved 4 ocs4 r/w 0 = disables the pull-down resistor on the ocs4 pin. 1 = enables the pull-down resistor on the ocs4 pin. 3 ocs3 r/w 0 = disables the pull-down resistor on the ocs3 pin. 1 = enables the pull-down resistor on the ocs3 pin. 2 ocs2 r/w 0 = disables the pull-down resistor on the ocs2 pin. 1 = enables the pull-down resistor on the ocs2 pin. 1 ocs1 r/w 0 = disables the pull-down resistor on the ocs1 pin. 1 = enables the pull-down resistor on the ocs1 pin. 0 vbus r/w 0 = disables the pull-down resistor on the vbus pin. 1 = enables the pull-down resistor on the vbus pin. table 5-24: led0 pull-down register led0_pd (0 x 082f) led0 pull-down register bit name r/w description 7:1 reserved r/w reserved. 0 led0 r/w 0 = disables the pull-down resistor on the led0 pin. 1 = enables the pull-down resistor on the led0 pin. table 5-25: vbus and ocs direction register vbus_ocs_dir (0 x 0831) vbus and ocs direction register bit name r/w description 7:5 reserved r/w reserved 4 ocs4 r/w direction: 0 = in, 1 = out. 3 ocs3 r/w direction: 0 = in, 1 = out. 2 ocs2 r/w direction: 0 = in, 1 = out. 1 ocs1 r/w direction: 0 = in, 1 = out. 0 vbus r/w direction: 0 = in, 1 = out. downloaded from: http:/// usb5537b ds00001682c-page 42 ? 2012 - 2015 microchip technology inc. 5.6.9 led0 direction register 5.6.10 vbus and ocs output register 5.6.11 led0 output register table 5-26: led0 direction register led0_dir (0 x 0833) led0 direction register 1 bit name r/w description 7:1 reserved r/w reserved 0 led0 r/w direction: 0 = in, 1 = out. table 5-27: vbus and ocs output register vbus_ocs_out (0 x 0835) vbus and ocs register bit name r/w description 7:5 reserved r/w reserved 4 ocs4 r/w output buffer data. 3 ocs3 r/w output buffer data. 2 ocs2 r/w output buffer data. 1 ocs1 r/w output buffer data. 0 vbus r/w output buffer data. table 5-28: led0 output register led0_out (0 x 0837) led0 output register bit name r/w description 7:1 reserved r/w reserved 0 led0 r/w pio0 output buffer data. this bit has no meaning if pio0 is in led mode. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 43 usb5537b 5.6.12 vbus and oc s input register 5.6.13 led0 input register 5.6.14 vbus and ocs pull- up resistor register table 5-29: vbus and ocs input register vbus_ocs_in (0 x 0839) vbus and ocs input register bit name r/w description 7:5 reserved r reserved 4 ocs4 r input buffer data. 3 ocs3 r input buffer data. 2 ocs2 r input buffer data. 1 ocs1 r input buffer data. 0 vbus r input buffer data. table 5-30: led0 input register led0_in (0 x 083b) led0 input register bit name r/w description 7:1 reserved r reserved 0 led0 r pio0 input buffer data. this bit is not valid if pio0 is in led mode. table 5-31: vbus and ocs pu ll-up resistor register vbus_ocs_pu (0 x 083d) vbus and ocs pull-up register bit name r/w description 7:5 reserved r/w reserved 4 ocs4 r/w 0 = disables the pull-up resistor on the ocs4 pin. 1 = enables the pull-up resistor on the ocs4 pin. 3 ocs3 r/w 0 = disables the pull-up resistor on the ocs3 pin. 1 = enables the pull-up resistor on the ocs3 pin. 2 ocs2 r/w 0 = disables the pull-up resistor on the ocs2 pin. 1 = enables the pull-up resistor on the ocs2 pin. 1 ocs1 r/w 0 = disables the pull-up resistor on the ocs1 pin. 1 = enables the pull-up resistor on the ocs1 pin. 0 vbus r/w 0 = disables the pull-up resistor on the vbus pin. 1 = enables the pull-up resistor on the vbus pin. downloaded from: http:/// usb5537b ds00001682c-page 44 ? 2012 - 2015 microchip technology inc. 5.6.15 led0 pull-up resistor register 5.6.16 port power pull-d own resistor register 5.6.17 port power direction register 5.6.18 port power output register table 5-32: led0 pull-up resistor register led0_pu (0 x 083f) led0 pull-up register bit name r/w description 7:1 reserved r/w reserved 0 led0 r/w 0 = disables the pull-up resistor on the led0 pin. 1 = enables the pull-up resistor on the led0 pin. table 5-33: port power pull- down resistor register prt_pwr_pd (0 x 092e) port power pull-down register bit name r/w description 7:1 prt_pwr_pd[7:1] r/w 0 = disables the pull-dow n resistor on the prt_pwr[n] pad. where n is the bit being controlled. bit 1 controls prt_pwr 1 and so on. 1 = enables the pull-down re sistor on the prt_pwr[n] pad. 0 reserved r/w reserved table 5-34: port power direction register prt_pwr_dir (0 x 0932) port power direction register bit name r/w description 7:1 prt_pwr_d[7:1] r/w prt_pwr[7:1] direction: 0 = in, 1 = out. 0 reserved r/w reserved table 5-35: port power output register prt_pwr_out (0 x 0936) port power output register bit name r/w description 7:1 prt_pwr_o[7:1] r/w prt_pwr[ 7:1] output buffer data. 0 reserved r/w reserved downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 45 usb5537b 5.6.19 port power input register 5.6.20 port power pull -up resistor register 5.6.21 port 1 power select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. table 5-36: port power input register prt_pwr_in (0 x 093a) port power input register bit name r/w description 7:1 prt_pwr[7:1] r prt[7:1] input buffer data. 0 reserved r reserved table 5-37: port power pu ll-up resistor register prt_pwr_pu(0 x 093e) port power pull up register bit name r/w description 7:1 prt_pwr_pu[7:1] r/w 0 = disables the pull-up re sistor on the prt_pwr[n] pad. where n is the bit being controlled. bit 1 controls prt_pwr 1 and so on. 1 = enables the pull-up resistor on the pio pad. 0 reserved r reserved table 5-38: port 1 power select register prt_pwr_sel1 (0 x 3c00) port 1 power select bit name r/w description 7 combined_mode r/w 0 - the port power and over-current sense use separate pins. 1 - the port power and over-current sense use the same pins. 6 reserved r reserved 5 disabled r/w when set this disables the port. used to inform the hub a port is permanently disabled. 4 nr_device r/w when set indicates this port has a permanently attached device. 3:0 prt_sel r/w this selects the source for the port power for port1 0000b - port power is disabled for this port. 0001b - port is on if usb2 port power is on 0010b - port is on if usb3 port power is on 0011b - port is on if usb2 or usb3 port power is on 0100b - port is on if designated gpio is on all other values are reserved. note: the port disable, port non-removable and combined mode bits must be set through a configuration file to ensure functionality when the part enumerates. downloaded from: http:/// usb5537b ds00001682c-page 46 ? 2012 - 2015 microchip technology inc. 5.6.22 port 2 power select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 5.6.23 port 3 power select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. table 5-39: port 2 power select register prt_pwr_sel2 (0 x 3c04) port 2 power select bit name r/w description 7 combined_mode r/w 0 - the port power and over-current sense use separate pins. 1 - the port power and over-current sense use the same pins. 6 reserved r reserved 5 disabled r/w when set this disables the port. used to inform the hub a port is permanently disabled. 4 nr_device r/w when set indicates this port has a permanently attached device. 3:0 prt_sel r/w this selects the source for the port power for port1 0000b - port power is disabled for this port. 0001b - port is on if usb2 port power is on 0010b - port is on if usb3 port power is on 0011b - port is on if usb2 or usb3 port power is on 0100b - port is on if designated gpio is on all other values are reserved. note: the port disable, port non-removable and combined mode bits must be set through a configuration file to ensure functionality when the part enumerates. table 5-40: port 3 power select register prt_pwr_sel3 (0 x 3c08) port 3 power select bit name r/w description 7 combined_mode r/w 0 - the port power and over-current sense use separate pins. 1 - the port power and over-current sense use the same pins. 6 reserved r reserved 5 disabled r/w when set this disables the port. used to inform the hub a port is permanently disabled. 4 nr_device r/w when set indicates this port has a permanently attached device. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 47 usb5537b 5.6.24 port 4 power select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 3:0 prt_sel r/w this selects the source for the port power for port1 0000b - port power is disabled for this port. 0001b - port is on if usb2 port power is on 0010b - port is on if usb3 port power is on 0011b - port is on if usb2 or usb3 port power is on 0100b - port is on if designated gpio is on all other values are reserved. note: the port disable, port non-removable and combined mode bits must be set through a configuration file to ensure functionality when the part enumerates. table 5-41: port 4 power select register prt_pwr_sel4 (0 x 3c0c) port 4 power select bit name r/w description 7 combined_mode r/w 0 - the port power and over-current sense use separate pins. 1 - the port power and over-current sense use the same pins. 6 reserved r reserved 5 disabled r/w when set this disables the port. used to inform the hub a port is permanently disabled. 4 nr_device r/w when set indicates this port has a permanently attached device. 3:0 prt_sel r/w this selects the source for the port power for port1 0000b - port power is disabled for this port. 0001b - port is on if usb2 port power is on 0010b - port is on if usb3 port power is on 0011b - port is on if usb2 or usb3 port power is on 0100b - port is on if designated gpio is on all other values are reserved. note: the port disable, port non-removable and combined mode bits must be set through a configuration file to ensure functionality when the part enumerates. table 5-40: port 3 power select register (continued) prt_pwr_sel3 (0 x 3c08) port 3 power select bit name r/w description downloaded from: http:/// usb5537b ds00001682c-page 48 ? 2012 - 2015 microchip technology inc. 5.6.25 port 5 power select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 5.6.26 port 6 power select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. table 5-42: port 5 power select register prt_pwr_sel5 (0 x 3c10) port 5 power select bit name r/w description 7 combined_mode r/w 0 - the port power and over-current sense use separate pins. 1 - the port power and over-current sense use the same pins. 6 reserved r reserved 5 disabled r/w when set this disables the port. used to inform the hub a port is permanently disabled. 4 nr_device r/w when set indicates this port has a permanently attached device. 3:0 prt_sel r/w this selects the source for the port power for port1 0000b - port power is disabled for this port. 0001b - port is on if usb2 port power is on 0010b - port is on if usb3 port power is on 0011b - port is on if usb2 or usb3 port power is on 0100b - port is on if designated gpio is on all other values are reserved. note: the port disable, port non-removable and combined mode bits must be set through a configuration file to ensure functionality when the part enumerates. table 5-43: port 6 power select register prt_pwr_sel6 (0 x 3c14) port 6 power select bit name r/w description 7 combined_mode r/w 0 - the port power and over-current sense use separate pins. 1 - the port power and over-current sense use the same pins. 6 reserved r reserved 5 disabled r/w when set this disables the port. used to inform the hub a port is permanently disabled. 4 nr_device r/w when set indicates this port has a permanently attached device. 3:0 prt_sel r/w this selects the source for the port power for port1 0000b - port power is disabled for this port. 0001b - port is on if usb2 port power is on 0010b - port is on if usb3 port power is on 0011b - port is on if usb2 or usb3 port power is on 0100b - port is on if designated gpio is on all other values are reserved. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 49 usb5537b 5.6.27 port 7 power select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 5.6.28 port 1 oc s select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. note: the port disable, port non-removable and combined mode bits must be set through a configuration file to ensure functionality when the part enumerates. table 1: port 7 power select register prt_pwr_sel7 (0 x 3c18) port 7 power select bit name r/w description 7 combined_mode r/w 0 - the port power and over-current sense use separate pins. 1 - the port power and over-current sense use the same pins. 6 reserved r reserved 5 disabled r/w when set this disables the port. used to inform the hub a port is permanently disabled. 4 nr_device r/w when set indicates this port has a permanently attached device. 3:0 prt_sel r/w this selects the source for the port power for port1 0000b - port power is disabled for this port. 0001b - port is on if usb2 port power is on 0010b - port is on if usb3 port power is on 0011b - port is on if usb2 or usb3 port power is on 0100b - port is on if designated gpio is on all other values are reserved. note: the port disable, port non-removable and combined mode bits must be set through a configuration file to ensure functionality when the part enumerates. table 5-44: port 1 ocs select register ocs_cfg_sel1 (0 x 3c20) port 1 ocs select bit name r/w description 7:4 reserved r/w reserved. 3:0 ocs_sel r/w this selects the source for the port power for port1 0000b - the port is disabled 0001b - ocs comes from ocs pin 0010b - ocs comes from gpio 1111b - ocs is force on (for testing) all other values are reserved. downloaded from: http:/// usb5537b ds00001682c-page 50 ? 2012 - 2015 microchip technology inc. 5.6.29 port 2 oc s select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 5.6.30 port 3 oc s select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. table 5-45: port 2 ocs select register ocs_cfg_sel2 (0 x 3c24) port 2 ocs select bit name r/w description 7:4 reserved r/w reserved. 3:0 ocs_sel r/w this selects the source for the port power for port1 0000b - the port is disabled 0001b - ocs comes from ocs pin 0010b - ocs comes from gpio 1111b - ocs is force on (for testing) all other values are reserved. table 5-46: port 3 ocs select register ocs_cfg_sel3 (0 x 3c28) port 3 ocs select bit name r/w description 7:4 reserved r/w reserved. 3:0 ocs_sel r/w this selects the source for the port power for port1 0000b - the port is disabled 0001b - ocs comes from ocs pin 0010b - ocs comes from gpio 1111b - ocs is force on (for testing) all other values are reserved. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 51 usb5537b 5.6.31 port 4 oc s select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 5.6.32 port 5 oc s select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. table 5-47: port 4 ocs select register ocs_cfg_sel4 (0 x 3c2c) port 4 ocs select bit name r/w description 7:4 reserved r/w reserved. 3:0 ocs_sel r/w this selects the source for the port power for port1 0000b - the port is disabled 0001b - ocs comes from ocs pin 0010b - ocs comes from gpio 1111b - ocs is force on (for testing) all other values are reserved. table 5-48: port 5 ocs select register ocs_cfg_sel5 (0 x 3c30) port 5 ocs select bit name r/w description 7:4 reserved r/w reserved. 3:0 ocs_sel r/w this selects the source for the port power for port1 0000b - the port is disabled 0001b - ocs comes from ocs pin 0010b - ocs comes from gpio 1111b - ocs is force on (for testing) all other values are reserved. downloaded from: http:/// usb5537b ds00001682c-page 52 ? 2012 - 2015 microchip technology inc. 5.6.33 port 6 oc s select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 5.6.34 port 7 oc s select register the bits in this register are configur ed via a configuration file. users must not change the values of these settings dynamically. 5.6.35 charging downstream detected register table 5-49: port 6 ocs select register ocs_cfg_sel6 (0 x 3c34) port 6 ocs select bit name r/w description 7:4 reserved r/w reserved. 3:0 ocs_sel r/w this selects the source for the port power for port1 0000b - the port is disabled 0001b - ocs comes from ocs pin 0010b - ocs comes from gpio 1111b - ocs is force on (for testing) all other values are reserved. table 5-50: port 7 ocs select register ocs_cfg_sel7 (0 x 3c38) port 7 ocs select bit name r/w description 7:4 reserved r/w reserved. 3:0 ocs_sel r/w this selects the source for the port power for port1 0000b - the port is disabled 0001b - ocs comes from ocs pin 0010b - ocs comes from gpio 1111b - ocs is force on (for testing) all other values are reserved. table 5-51: charging downstream detected register cdp_detect (0 x 5246) charging downstream detected bit name r/w description 7 reserved r/w reserved 6 p7_cdp r/w 0 = no cdp handshake detected. 1 = charging downstream port handshake detected prior to enumeration. 5 p6_cdp r/w 0 = no cdp handshake detected. 1 = charging downstream port handshake detected prior to enumeration. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 53 usb5537b 5.6.36 ocs gang control register 4 p5_cdp r/w 0 = no cdp handshake detected. 1 = charging downstream port handshake detected prior to enumeration. 3 p4_cdp r/w 0 = no cdp handshake detected. 1 = charging downstream port handshake detected prior to enumeration. 2 p3_cdp r/w 0 = no cdp handshake detected. 1 = charging downstream port handshake detected prior to enumeration. 1 p2_cdp r/w 0 = no cdp handshake detected. 1 = charging downstream port handshake detected prior to enumeration. 0 p1_cdp r/w 0 = no cdp handshake detected. 1 = charging downstream port handshake detected prior to enumeration. table 5-52: ocs gang control register ocs_gang (0 x 525a) ocs gang control bit name r/w description 7 p7_ocs_gang r/w setting this bit to 1 will caus e this ports ocs status to be ganged to the selected pin. 6 p6_ocs_gang r/w setting this bit to 1 will caus e this ports ocs status to be ganged to the selected pin. 5 p5_ocs_gang r/w setting this bit to 1 will caus e this ports ocs status to be ganged to the selected pin. 4 p4_ocs_gang r/w setting this bit to 1 will caus e this ports ocs status to be ganged to the selected pin. 3 p3_ocs_gang r/w setting this bit to 1 will caus e this ports ocs status to be ganged to the selected pin. 2 p2_ocs_gang r/w setting this bit to 1 will caus e this ports ocs status to be ganged to the selected pin. 1 p1_ocs_gang r/w setting this bit to 1 will caus e this ports ocs status to be ganged to the selected pin. 0 reserved r/w reserved table 5-51: charging downstream detected register (continued) cdp_detect (0 x 5246) charging downstream detected bit name r/w description downloaded from: http:/// usb5537b ds00001682c-page 54 ? 2012 - 2015 microchip technology inc. 5.6.37 ocs gang sign al select register 5.6.38 usb upstream boost register table 5-53: ocs gang signal select register ocs_gang_gpio (0 x 525b) ocs gang control bit name r/w description 7:6 reserved r/w reserved 5:0 ganged_ocs_ signal r/w only the following configur ations are valid settings: 0 = trst 1 = ocs1 3 = ocs2 4 = spi_clk 5 = spi_do 6 = ocs3 7 = ocs4 8 = prtctl1 9 = prtctl2 10 = prtctl3 11 = prtctl4 12 = prtctl5 13 = prtctl6 14 = prtctl7 15 = sm_clk table 5-54: usb upstream boost register hs_up_boost (0 x 60ca) usb upstream boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 55 usb5537b 5.6.39 usb upstream varisense register 5.6.40 usb3 upstream link state register 5.6.41 usb port 1 boost register table 5-55: usb upstream varisense register phy_up_sense (0 x 60cc) usb upstream varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 5-56: usb3 upstream link state register ss_up_state (0 x 61c0) usb3 upstream link state bit name r/w description 7:4 link_state r refer to table 5-74, "usb 3.0 link states" for more details. 3 reserved r reserved 2:0 link_sub_state r refer to table 5-74, "usb 3.0 link states" for more details. table 5-57: usb port 1 boost register hs_p1_boost (0 x 64ca) usb port 1 boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// usb5537b ds00001682c-page 56 ? 2012 - 2015 microchip technology inc. 5.6.42 usb port 1 varisense register 5.6.43 usb3 port 1 link state 5.6.44 usb port 2 boost register table 5-58: usb port 1 varisense register phy_p1_sense (0 x 64cc) usb port 1 varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 5-59: usb3 port 1 link state ss_p1_state (0 x 65c0) usb3 port1 link state bit name r/w description 7:4 link_state r refer to table 5-74, "usb 3.0 link states" for more details. 3 reserved r reserved 2:0 link_sub_state r refer to table 5-74, "usb 3.0 link states" for more details. table 5-60: usb port 2 boost register hs_p2_boost (0 x 68ca) usb port 2 boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 57 usb5537b 5.6.45 usb port 2 varisense register 5.6.46 usb3 port 2 link state 5.6.47 usb port 3 boost register table 5-61: usb port 2 varisense register phy_p2_sense (0 x 68cc) usb port 2 varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 5-62: usb3 port 2 link state ss_p2_state (0 x 69c0) usb3 port 2 link state bit name r/w description 7:4 link_state r refer to table 5-74, "usb 3.0 link states" for more details. 3 reserved r reserved 2:0 link_sub_state r refer to table 5-74, "usb 3.0 link states" for more details. table 5-63: usb port 3 boost register hs_p3_boost (0 x 6cca) usb port 3 boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// usb5537b ds00001682c-page 58 ? 2012 - 2015 microchip technology inc. 5.6.48 usb port 3 varisense register 5.6.49 usb3 port 3 link state 5.6.50 usb port 4 boost register table 5-64: usb port 3 varisense register phy_p3_sense (0 x 6ccc) usb port 3 varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 5-65: usb3 port 3 link state ss_p3_state (0 x 6dc0) usb3 port 3 link state bit name r/w description 7:4 link_state r refer to table 5-74, "usb 3.0 link states" for more details. 3 reserved r reserved 2:0 link_sub_state r refer to table 5-74, "usb 3.0 link states" for more details. table 5-66: usb port 4 boost register hs_p4_boost (0 x 70ca) usb port 4 boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 59 usb5537b 5.6.51 usb port 4 varisense register 5.6.52 usb3 port 4 link state register 5.6.53 usb port 5 boost register table 5-67: usb port 4 varisense register phy_p4_sense (0 x 70cc) usb port 4 varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 5-68: usb3 port 4 link state register ss_p4_state (0 x 71c0) usb3 port 4 link state bit name r/w description 7:4 link_state r refer to table 5-74, "usb 3.0 link states" for more details. 3 reserved r reserved 2:0 link_sub_state r refer to table 5-74, "usb 3.0 link states" for more details. table 5-69: usb port 5 boost register hs_p5_boost (0 x 74ca) usb port 4 boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// usb5537b ds00001682c-page 60 ? 2012 - 2015 microchip technology inc. 5.6.54 usb port 5 varisense register 5.6.55 usb port 6 boost register table 5-70: usb port 5 varisense register phy_p5_sense (0 x 74cc) usb port 5 varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 5-71: usb port 6 boost register hs_p6_boost (0 x 78ca) usb port 6 boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 61 usb5537b 5.6.56 usb port 6 varisense register 5.6.57 usb port 7 boost register table 5-72: usb port 6 varisense register phy_p6_sense (0 x 78cc) usb port 6 varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 2: usb port 7 boost register hs_p7_boost (0 x 7cca) usb port 7 boost register bit name r/w description 7:3 reserved r/w reserved 2:0 hs_boost r/w hs output current. 3b000: nominal 3b001: decrease by 5% 3b010: increase by 10% 3b011: increase by 5% 3b100: increase by 20% 3b101: increase by 15% 3b110: increase by 30% 3b111: increase by 25% downloaded from: http:/// usb5537b ds00001682c-page 62 ? 2012 - 2015 microchip technology inc. 5.6.58 usb port 7 varisense register table 5-73: usb port 7 varisense register phy_p4_sense (0 x 7ccc) usb port 7 varisense register bit name r/w description 7:3 reserved r reserved 2:0 hs_sq_tune[2:0] r/w squelch tune 3b000: nominal 100mv trip point 3b001: decrease by 12.5mv 3b010: decrease by 25mv 3b011: decrease by 37.5mv 3b100: decrease by 50mv 3b101: decrease by 62.5mv 3b110: increase by 25mv 3b111: increase by 12.5mv table 5-74: usb 3.0 link states num link state 00h u0 01h u1 02h u2 03h u3 04h sis.disabled 05h rx.detect 06h ss.inactive 07h polling 08h recovery 09h hot reset 0ah compliance 0bh loopback downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 63 usb5537b 6.0 dc parameters 6.1 maximum ratings note 1: stresses above the specified parameters could cause pe rmanent damage to the device. this is a stress rat- ing only. therefore, functional oper ation of the device at any condition above those indicated in the operation sections of this specif ication are not implied. 2: when powering this device from laboratory or system powe r supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. when this possibility ex ists, it is suggested that a clamp circuit be used. 6.2 operating conditions parameter symbol min max units comments storage temperature t a -55 150 c lead temperature c refer to jedec specification j-std- 020d. 1.25 v supply voltage v dd12 -0.5 1.6 v 3.3 v supply voltage v dd33 -0.5 4.0 v voltage on usb+ and usb- pins -0.5 (3.3 v supply voltage + 2) ?? 6 v voltage on any signal powered by vdd33 rail -0.5 v dd33 + 0.3 v voltage on any signal pin powered by the vdd12 -0.5 vdd12 + 0.3 v hbm esd performance 2k v power consumption 2.0 w parameter symbol min max units comments usb5537b operating temperature t a 07 0 c die temperature t j 115 c 1.25 v supply voltage v dd12 1.22 1.31 v 3.3 v supply voltage v dd33 3.0 3.6 v 1.25 v supply rise time t rt 04 0 0 ? s( table 6-1 ) 3.3 v supply rise time t rt 04 0 0 ? s( table 6-1 ) voltage on usb+ and usb- pins -0.3 5.5 v if any 3.3 v supply voltage drops below 3.0 v, then the max becomes: (3.3 v supply voltage) + 0.5 ? 5.5 voltage on any signal powered by vdd33 rail -0.3 v dd33 v downloaded from: http:/// usb5537b ds00001682c-page 64 ? 2012 - 2015 microchip technology inc. 6.3 power consumption this section details the power consumption of the device as measured during various modes of operation. all typical measurements were taken with power supplies at nominal values (vdd12 = 1.25 v, vdd33 = 3.3 v). note 6-1 the global suspend typical supply current and power are stated for device versions -6070 and -6080. version -5000 has a typical supply current of 17 ma for vdd33, 28 ma for vdd12, and 91 mw of total power consumption. table 6-1: supply rise time model typical supply current (ma) typical power (mw) vdd33 vdd12 reset 0.2 5.0 6.9 no vbus 9.1 23.0 58.8 global suspend ( note 6-1 ) 1.1 8.3 14.0 7 fs ports 40 78 230 7 hs ports 64 91 325 4 ss ports 25 1121 1484 4 ss / 7 hs ports 73 1173 1707 t 10% 10% 90% voltage t rtxx t 90% time 100% 3.3 v vss vdd33 90% 100% 1.25 v vdd12 downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 65 usb5537b 6.4 dc electrical characteristics note 6-2 output leakage is measured with th e current pins in high impedance. note 6-3 see usb 2.0 specification 1. for usb dc electrical characteristics. table 6-2: dc electrical characteristics parameter symbol min typ max units comments is type input buffer low input level v ili 0.8 v ttl levels high input level v ihi 2.0 v hysteresis (is only) v hysi 420 mv i, ipu, ipd type input buffer low input level v ili 0.8 v ttl levels high input level v ihi 2.0 v pull down pd 72 ? av in = 0 pull up pu 58 ? av in = vdd33 iclk input buffer low input level v ilck 0.3 v high input level v ihck 0.8 v input leakage i il -10 +10 ? av in = 0 to vdd33 input leakage (all i and is buffers) low input leakage i il -10 +10 ? av in = 0 high input leakage i ih -10 +10 ? av in = vdd33 o12 type buffer low output level v ol 0.4 v i ol = 12 ma @ vdd33 = 3.3 v high output level v oh v dd33 -0.4 vi oh = -12 ma @ vdd33 = 3.3 v output leakage i ol -10 +10 ? av in = 0 to vdd33 ( note 6-2 ) i/o12, i/o12pu & i/o12pd type buffer low output level v ol 0.4 v i ol = 12 ma @ vdd33 = 3.3 v high output level v oh v dd33 -0.4 vi oh = -12 ma @ vdd33 = 3.3 v output leakage i ol -10 +10 ? av in = 0 to vdd33 ( note 6-2 ) pull down pd 72 ? a pull up pu 58 ? a io-u ( note 6-3 ) downloaded from: http:/// usb5537b ds00001682c-page 66 ? 2012 - 2015 microchip technology inc. 6.5 capacitance note 6-4 capacitance t a = 25c; fc = 1 mhz; vdd33 = 3.3 v 6.5.1 package thermal specifications thermal parameters are measured or estimated for devices with the exposed pad soldered to thermal vias in a multi- layer 2s2p pcb per jesd51. thermal resistance is measured from the die to the ambient air. the values provided are based on the package body, die size, maximum power consum ption, 70c ambient temp erature, and 125c junction temperature of the die. use the following formulas to calc ulate the junction temperature: tj = p x ? ja + ta tj = p x ? jt + tt tj = p x ? jc + tc table 6-3: pin capacitance limits parameter symbol min typ max unit test condition clock input capacitance c xtal 2 pf all pins except usb pins and the pins under the test tied to ac ground input capacitance c in 5p f output capacitance c out 10 pf symbol usb5537b (c/w) velocity (meter/s) ? ja 22.2 0 ? jt 0.1 0 ? jc 1.4 0 symbol description t j junction temperature p power dissipated ? ja junction-to-ambient-temperature ? jc junction-to-top-of-package ? jt junction-to-bottom-of-case t a ambient temperature t c temperature of the bottom of the case t t temperature of the top of the case downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 67 usb5537b 7.0 ac specifications 7.1 oscillator/crystal crystal: parallel resonant, fundamental mode, 25 mhz ? 30 ppm external clock: 50% duty cycle ? 10%, 25 mhz ? 30 ppm, jitter < 100 ps rms note 7-1 c 0 is usually included (subtracted by the crystal manufacturer) in the specification for c l and should be set to 0 for use in the calculation of the capacitance formulas in figure 7-2 . however, the pcb itself may present a parasitic capacitance between xtalin and xtalout . for an accurate calculation of c 1 and c 2 , take the parasitic capacitance between traces xtalin and xtalout into account. note 7-2 consult crystal manufacturer documentation for recommended capacitance values. figure 7-1: typical crystal circuit table 7-1: crystal circuit legend symbol description in accordance with c 0 crystal shunt capacitance crystal manufacturer s specification ( note 7-1 ) c l crystal load capacitance c b total board or trace capacitance oem board design c s stray capacitance microchip ic and oem board design c xtal xtal pin input capacitance microchip ic c 1 load capacitors installed on oem board calculated values based on figure 7-2 ( note 7-2 ) c 2 figure 7-2: formula to find the value of c 1 and c 2 c 1 c 2 c l crystal xtal2 (c s2 = c b2 + c xtal2 ) xtal1 (c s1 = c b1 + c xtal1 ) c 0 c 1 = 2 x (c l C c 0 ) C c s1 c 2 = 2 x (c l C c 0 ) C c s2 downloaded from: http:/// usb5537b ds00001682c-page 68 ? 2012 - 2015 microchip technology inc. 7.2 external clock 50% duty cycle ? 10%, 25 mhz ? 30 ppm, jitter < 100 ps rms. 7.2.1 smbus clock the maximum frequency allowed on the smbus clock line is 100 khz. 7.2.2 usb 2.0 bit the microchip hub conforms to all voltage, power, and ti ming characteristics and specifications as set forth in the usb 2.0 specification 1. 7.3 spi timing note: the external clock is based upon 1.2 v cmos logic. xtalout should be treated as a no connect when an external clock is supplied. figure 7-3: spi timing table 7-2: spi timing operation name parameter min max unit t fc clock frequency 60 mhz t ceh chip enable high time 50 ns t clq clock to input data 9 ns t dh input data hold time 0 ns t os output set up time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns spi_cen spi_clk spi_di spi_do t dh input data valid t clq output data valid t ov t oh output data valid t os t oh t fc t ceh downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 69 usb5537b 7.4 smbus timing the smbus slave interface complies with the smbus specification revision 1.0 . see section 2.1, ac specifications on page 3 for more information. figure 7-4: smbus slave timing diagram table 7-3: smbus slave timing modes symbol paramete rm i n m a x u n i t f scl sm_clk clock frequency 0 100 khz t hd;sta hold time start condition 4 - ? s t low low period of the sm_clk clock 4.7 - ? s t high high period of the sm_clk clock 4 - ? s t su;sta set-up time for a repeated start condition 4.7 - ? s t hd;dat data hold time\ 0 - ns t su;dat data set-up time 250 - ns t r rise time of both sm_data and sm_clk signals - 1000 ns t f fall time of both sm_clk and sm_data lines - 300 ns t su;sto set-up time for a stop condition 4 - ? s t buf bus free time between a stop and start condition 4.7 - ? s sm_data sm_clk t buf t hd;sta t su;sto t su;sta t su;dat t high t hd;dat t hd;sta t low t r t f downloaded from: http:/// usb5537b ds00001682c-page 70 ? 2012 - 2015 microchip technology inc. 8.0 package drawing figure 8-1: usb5537b 72-pin qfn package outline note: for the most current package draings, see the microchip packaging specification at http://.microchip.com/packaging downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 71 usb5537b figure 8-1: usb5537b 72-pin qfn package outline (continued) note: for the most current package draings, see the microchip packaging specification at http://.microchip.com/packaging downloaded from: http:/// usb5537b ds00001682c-page 72 ? 2012 - 2015 microchip technology inc. appendix a: data sheet revision history table a-1: data sheet revision history revision level & date section/figure/entry correction ds00001682c (10-12-15) "product identification system" ordering information corrected. ds00001682b (09-26-14) document is converted to microchip template overview on page 4 usb 2.0 added following mention of multitrak technology, portswap and phyboost. cover references to 8k ram changed to 8 kb ram and references to 32 k rom changed to 32 kb rom. second paragraph in general description modified. section 3.2, "pin descriptions (grouped by function)," on page 8 corrected prt_pwr x /prt_ctl x pin description to include cross-reference note. figure 3-1: usb5537b 72- pin qfn on page 7 updated prt_pwr x /prt_ctl x pin names to include both primary and secondary functions. section 3.2, "pin descriptions (grouped by function)," on page 8 provided additional vbus pin description information for clarity. section 4.2, "smbus slave interface," on page 18 in second paragraph, updated sentence to disable the smbus, a pull-down resistor of 10 10 k ? must be applied to sm_dat . to: to disable the smbus, a pull-down resistor of 10 k ? must be applied to either sm_dat , sm_clk , or both sm_dat and sm_clk if desired. all added -6070 ordering option and information throughout document. rev a (02-27-14) replaces previous smsc vers ion 1.3; document ha s been microchip branded general description on cover: legacy is replaced with non-usb 1.2 rev. 1.3 (01-23-14) all added -6080 firmware ordering code and info throughout document. introduction on page 4 added information on the -5000 vs. -6080 firmware differences. section 6.5.1, "package thermal specifications," on page 66 added package thermal specifications. functional operation on page 24 renamed chapter. updated entire chapter with additional information on battery charging, configuration options, otp, and external spi operation, runtime register definitions, etc. standard interface connections on page 13 renamed chapter. added non-bc power configuration and battery charging sections. pin information on page 7 added alternate functions to trst pin. section 6.3, "power consumption," on page 64 updated power consumption values. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 73 usb5537b rev. 1.2 (05-31-13) all removed industrial temp. sku information from document. section 6.1, "maximum ratings," on page 63 added maximum power consumption row/data to table. section 6.2, "operating conditions," on page 63 added maximum die temperature row/data to table. section 6.3, "power consumption," on page 64 updated power consumption numbers note 3-1 on page 11 and note 3-3 on page 11 updated note to reflect configuration straps are enabled by default. pin information on page 7 updated trst pin description with the following note: if using the smbus interface, a pull-up on this signal will enable legacy mode, while leaving it unconnected or pulled-down will enable advanced mode. package drawing on page 70 updated recommended land pattern drawings and information. rev. 1.1 (03-05-13) ordering codes updated ordering codes to for a2 material ordering codes corrected tape and reel quantity from 3000 to 2500. section 3.2, "pin descriptions (grouped by function)," on page 8 added note 3-1 and note 3-3 explaining the configuration strap functions on the prt_pwrx and ocsx pins. section 6.3, "power consumption," on page 64 added power consumption section and values section 4.1.2, "operation of the dual hi-speed read sequence," on page 14 updated first sentence to state that dual data mode is supported only at an spi speed of 30 mhz standard interface connections on page 13 clarified interface ordering explanation. section 4.2, "smbus slave interface," on page 18 removed either an external i2c (if present) and from last sentence of section. section 4.2, "smbus slave interface," on page 18 added additional sentence: for operation in smbus legacy mode, an additional pull-up resistor is required on trst . section 5.5, "smbus slave interface," on page 29 , figure 5-6: smbus commands on page 30 , figure 5-5: block read on page 30 updated register address references to smbus ram buffer offset. spi_do pin description & added note to describe the spi_spd_sel configuration strap function on the spi_do. all removed references to gpios and leds rev. 1.0 (09-06-12) all initial revision. table a-1: data sheet revi sion histor y (continued) revision level & date section/figure/entry correction downloaded from: http:/// usb5537b ds00001682c-page 74 ? 2012 - 2015 microchip technology inc. appendix b: acronyms i 2 c ? : inter-integrated circuit 1 ocs: over-current sense pcb: printed circuit board phy: physical layer pll: phase-locked loop qfn: quad flat no leads rohs: restriction of hazardous substances directive scl: serial clock sie: serial interface engine smbus: system management bus tt: transaction translator 1. i 2 c is a registered trademark of philips corporation. downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 75 usb5537b appendix c: references 1. universal serial bus specification, version 2. 0, april 27, 2000 (12/7/2000 and 5/28/2002 errata) usb implementers forum, inc. http://www.usb.org 2. universal serial bus specificatio n, version 3.0, november 13, 2008 3. usb implementers forum, inc. http://www.usb.org 4. system management bus sp ecification, version 1.0 5. smbus. http://smbus.org/specs/ 6. microchip 24aa02/24lc02b (revision c) 7. microchip technology inc. http://www.microchip.com/ downloaded from: http:/// usb5537b ds00001682c-page 76 ? 2012 - 2015 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 77 usb5537b product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: usb5537b temperature range: blank = 0 ? c to +70 ? c commercial package: 5000akze = 72-pin qfn 10 x 10mm 6.0mm exposed pad hybrid 4/7-port hub with vsm, apple/bc 1.2 charging 6070akze = 72-pin qfn 10 x 10mm 6.0mm exposed pad hybrid 4/7-port hub with vsm, apple/bc 1.2 charging 6080akze = 72-pin qfn 10 x 10mm 6.0mm exposed pad hybrid 4/7-port hub with vsm, apple/bc 1.2 charging tape and reel option: blank = standard packaging (tray) tr = tape and reel (1) examples: a) usb5537b-5000akze b) usb5537b-6070akze c) usb5537b-6080akze note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sa les office for package availability with the tape and reel option. reel size is 4,000. part no. [x] xxx package temperature range device [x] (1) tape and reel option - - downloaded from: http:/// usb5537b ds00001682c-page 78 ? 2012 - 2015 microchip technology inc. information contained in this publication regarding device applications and the like is provided onl y for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specif ications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyers ri sk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such us e. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code genera tion, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock , wireless dna, and zena are trademarks of microchip technology incor porated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tec hnology inc. in other countries. gestic is a registered trademark of microc hip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., i n other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012 - 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781632778642 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner out side the operating specifications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the securi ty of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyright ed work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:/// ? 2012 - 2015 microchip technology inc. ds00001682c-page 79 americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 07/14/15 downloaded from: http:/// |
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